diff options
| -rw-r--r-- | src/simul/simul-vhdl_simul.adb | 194 | ||||
| -rw-r--r-- | src/synth/elab-vhdl_context.adb | 25 | ||||
| -rw-r--r-- | src/synth/elab-vhdl_context.ads | 22 | ||||
| -rw-r--r-- | src/synth/elab-vhdl_debug.adb | 2 | ||||
| -rw-r--r-- | src/synth/elab-vhdl_values-debug.adb | 3 | ||||
| -rw-r--r-- | src/synth/elab-vhdl_values.adb | 26 | ||||
| -rw-r--r-- | src/synth/elab-vhdl_values.ads | 13 | ||||
| -rw-r--r-- | src/synth/synth-vhdl_context.adb | 3 | ||||
| -rw-r--r-- | src/synth/synth-vhdl_expr.adb | 1 | ||||
| -rw-r--r-- | src/synth/synth-vhdl_insts.adb | 3 | ||||
| -rw-r--r-- | src/synth/synth-vhdl_stmts.adb | 34 | ||||
| -rw-r--r-- | src/synth/synth-vhdl_stmts.ads | 19 |
12 files changed, 294 insertions, 51 deletions
diff --git a/src/simul/simul-vhdl_simul.adb b/src/simul/simul-vhdl_simul.adb index 0ebb719f0..6e3d62e88 100644 --- a/src/simul/simul-vhdl_simul.adb +++ b/src/simul/simul-vhdl_simul.adb @@ -69,6 +69,9 @@ package body Simul.Vhdl_Simul is procedure Process_Executer (Self : Grt.Processes.Instance_Acc); pragma Convention (C, Process_Executer); + procedure Update_Signal_Individual_Assocs_Values + (Inst : Synth_Instance_Acc); + type Ghdl_Signal_Ptr_Ptr is access all Ghdl_Signal_Ptr; function To_Ghdl_Signal_Ptr_Ptr is new Ada.Unchecked_Conversion (Memory_Ptr, Ghdl_Signal_Ptr_Ptr); @@ -110,20 +113,32 @@ package body Simul.Vhdl_Simul is function Hook_Signal_Expr (Val : Valtyp) return Valtyp is begin - if Val.Val.Kind = Value_Alias then - declare - E : Signal_Entry renames Signals_Table.Table (Val.Val.A_Obj.S); - begin - return Create_Value_Memtyp - ((Val.Typ, E.Val + Val.Val.A_Off.Mem_Off)); - end; - else - declare - E : Signal_Entry renames Signals_Table.Table (Val.Val.S); - begin - return Create_Value_Memtyp ((E.Typ, E.Val)); - end; - end if; + case Val.Val.Kind is + when Value_Alias => + declare + E : Signal_Entry renames Signals_Table.Table (Val.Val.A_Obj.S); + begin + return Create_Value_Memtyp + ((Val.Typ, E.Val + Val.Val.A_Off.Mem_Off)); + end; + when Value_Signal => + declare + E : Signal_Entry renames Signals_Table.Table (Val.Val.S); + begin + return Create_Value_Memtyp ((E.Typ, E.Val)); + end; + when Value_Sig_Val => + return Create_Value_Memtyp ((Val.Typ, Val.Val.I_Vals)); + when Value_Net + | Value_Wire + | Value_Memory + | Value_File + | Value_Quantity + | Value_Terminal + | Value_Dyn_Alias + | Value_Const => + raise Internal_Error; + end case; end Hook_Signal_Expr; function Hook_Quantity_Expr (Val : Valtyp) return Valtyp is @@ -331,6 +346,29 @@ package body Simul.Vhdl_Simul is end loop; end Create_Process_Drivers; + function Get_Sig_Mem (Val : Value_Acc; Idx : Uns32) return Memory_Ptr + is + Base : Memory_Ptr; + begin + case Val.Kind is + when Value_Signal => + Base := Signals_Table.Table (Val.S).Sig; + when Value_Sig_Val => + Base := Val.I_Sigs; + when Value_Net + | Value_Wire + | Value_Memory + | Value_File + | Value_Quantity + | Value_Terminal + | Value_Const + | Value_Dyn_Alias + | Value_Alias => + raise Internal_Error; + end case; + return Sig_Index (Base, Idx); + end Get_Sig_Mem; + type Read_Signal_Flag_Enum is (Read_Signal_Event, Read_Signal_Active, @@ -407,10 +445,7 @@ package body Simul.Vhdl_Simul is pragma Assert (Pfx.Obj.Val /= null and then Pfx.Obj.Val.Kind = Value_Signal); E := Read_Signal_Flag - ((Pfx.Targ_Type, - Sig_Index (Signals_Table.Table (Pfx.Obj.Val.S).Sig, - Pfx.Off.Net_Off)), - Kind); + ((Pfx.Targ_Type, Get_Sig_Mem (Pfx.Obj.Val, Pfx.Off.Net_Off)), Kind); Res := Create_Value_Memory (Boolean_Type, Expr_Pool'Access); Write_U8 (Res.Val.Mem, Boolean'Pos (E)); return Res; @@ -696,9 +731,8 @@ package body Simul.Vhdl_Simul is while Is_Valid (It) loop El := Get_Element (It); Info := Synth_Target (Inst, El); - Sig := Signals_Table.Table (Info.Obj.Val.S).Sig; - Add_Wait_Sensitivity - (Info.Targ_Type, Sig_Index (Sig, Info.Off.Net_Off)); + Sig := Get_Sig_Mem (Info.Obj.Val, Info.Off.Net_Off); + Add_Wait_Sensitivity (Info.Targ_Type, Sig); Next (It); end loop; end; @@ -715,6 +749,21 @@ package body Simul.Vhdl_Simul is function Resume_Wait_Statement (Inst : Synth_Instance_Acc; Stmt : Node) return Boolean is begin + -- For all procedures in the activation chain, update individual + -- signal associations. + declare + Cinst : Synth_Instance_Acc; + begin + Cinst := Inst; + loop + if Get_Indiv_Signal_Assoc_Flag (Cinst) then + Update_Signal_Individual_Assocs_Values (Cinst); + end if; + exit when not Get_Indiv_Signal_Assoc_Parent_Flag (Cinst); + Cinst := Get_Instance_Parent (Cinst); + end loop; + end; + -- LRM93 8.1 -- The suspended process will resume, at the latest, immediately -- after the timeout interval has expired. @@ -2668,14 +2717,15 @@ package body Simul.Vhdl_Simul is end case; end Register_Prefix; - function Alloc_Signal_Memory (Vtype : Type_Acc) return Memory_Ptr + function Alloc_Signal_Memory + (Vtype : Type_Acc; Pool : Areapools.Areapool_Acc) return Memory_Ptr is function To_Memory_Ptr is new Ada.Unchecked_Conversion (System.Address, Memory_Ptr); M : System.Address; begin - Areapools.Allocate (Global_Pool, - M, Sig_Size * Size_Type (Vtype.W), Sig_Size); + Areapools.Allocate + (Pool.all, M, Sig_Size * Size_Type (Vtype.W), Sig_Size); return To_Memory_Ptr (M); end Alloc_Signal_Memory; @@ -2694,7 +2744,7 @@ package body Simul.Vhdl_Simul is E : Signal_Entry renames Signals_Table.Table (Idx); S : Ghdl_Signal_Ptr; begin - E.Sig := Alloc_Signal_Memory (E.Typ); + E.Sig := Alloc_Signal_Memory (E.Typ, Global_Pool'Access); case E.Kind is when Mode_Guard => Create_Guard_Signal (Idx); @@ -3089,7 +3139,7 @@ package body Simul.Vhdl_Simul is if Out_Conv /= Null_Node then -- From formal to actual. Ctyp := C.Actual.Typ; - Csig := Alloc_Signal_Memory (Ctyp); + Csig := Alloc_Signal_Memory (Ctyp, Global_Pool'Access); Cval := Alloc_Memory (Ctyp, Global_Pool'Access); Create_Shadow_Signal (Csig, Cval, Ctyp); Form2 := (Ctyp, Csig); @@ -3124,7 +3174,7 @@ package body Simul.Vhdl_Simul is if In_Conv /= Null_Node then Ctyp := C.Formal.Typ; - Csig := Alloc_Signal_Memory (Ctyp); + Csig := Alloc_Signal_Memory (Ctyp, Global_Pool'Access); Cval := Alloc_Memory (Ctyp, Global_Pool'Access); Create_Shadow_Signal (Csig, Cval, Ctyp); Act2 := (Ctyp, Csig); @@ -3223,8 +3273,93 @@ package body Simul.Vhdl_Simul is end loop; end Create_Connects; - procedure Create_Terminals + procedure Update_Sig_Val (Typ : Type_Acc; + Sigs : Memory_Ptr; + Vals : Memory_Ptr) is + Sig : Ghdl_Signal_Ptr; + begin + case Typ.Kind is + when Type_Logic + | Type_Bit + | Type_Discrete + | Type_Float => + Sig := Read_Sig (Sigs); + Write_Ghdl_Value ((Typ, Vals), Sig.Value_Ptr.all); + when Type_Vector + | Type_Array => + declare + Len : constant Uns32 := Typ.Abound.Len; + El : constant Type_Acc := Typ.Arr_El; + begin + for I in 1 .. Len loop + Update_Sig_Val (El, + Sig_Index (Sigs, (Len - I) * El.W), + Vals + Size_Type (I - 1) * El.Sz); + end loop; + end; + when Type_Record => + for I in Typ.Rec.E'Range loop + declare + E : Rec_El_Type renames Typ.Rec.E (I); + begin + Update_Sig_Val (E.Typ, + Sig_Index (Sigs, E.Offs.Net_Off), + Vals + E.Offs.Mem_Off); + end; + end loop; + when others => + raise Internal_Error; + end case; + end Update_Sig_Val; + + procedure Update_Signal_Individual_Assocs_Values (Inst : Synth_Instance_Acc) + is + Bod : constant Node := Get_Source_Scope (Inst); + Spec : constant Node := Get_Subprogram_Specification (Bod); + Inter : Node; + Obj : Valtyp; + begin + Inter := Get_Interface_Declaration_Chain (Spec); + while Inter /= Null_Node loop + Obj := Get_Value (Inst, Inter); + if Obj.Val.Kind = Value_Sig_Val then + Update_Sig_Val (Obj.Typ, Obj.Val.I_Sigs, Obj.Val.I_Vals); + end if; + Inter := Get_Chain (Inter); + end loop; + end Update_Signal_Individual_Assocs_Values; + + function Hook_Create_Value_For_Signal_Individual_Assocs + (Inst : Synth_Instance_Acc; + Assocs : Assoc_Array; + Typ : Type_Acc) return Valtyp + is + Sigs : Memory_Ptr; + Vals : Memory_Ptr; + begin + Set_Indiv_Signal_Assoc_Flag (Inst); + + Sigs := Alloc_Signal_Memory (Typ, Instance_Pool); + for I in Assocs'Range loop + declare + A : Assoc_Record renames Assocs (I); + begin + -- TODO: individual assoc using individual assoc formal. + Copy_Memory + (Sig_Index (Sigs, A.Form_Off.Net_Off), + Sig_Index (Exec_Sig_Sig (A.Act_Base.Val), A.Act_Off.Net_Off), + Size_Type (A.Act_Typ.W) * Sig_Size); + end; + end loop; + + Vals := Alloc_Memory (Typ, Instance_Pool); + Update_Sig_Val (Typ, Sigs, Vals); + + return Create_Value_Sig_Val (Sigs, Vals, Typ, Instance_Pool); + end Hook_Create_Value_For_Signal_Individual_Assocs; + + procedure Create_Terminals is begin for I in Terminal_Table.First .. Terminal_Table.Last loop declare @@ -3606,6 +3741,9 @@ package body Simul.Vhdl_Simul is Synth.Vhdl_Static_Proc.Hook_Finish := Exec_Finish'Access; + Synth.Vhdl_Stmts.Hook_Create_Value_For_Signal_Individual_Assocs := + Hook_Create_Value_For_Signal_Individual_Assocs'Access; + -- if Flag_Interractive then -- Debug (Reason_Elab); -- end if; diff --git a/src/synth/elab-vhdl_context.adb b/src/synth/elab-vhdl_context.adb index 136cc50f0..d77b8ea6e 100644 --- a/src/synth/elab-vhdl_context.adb +++ b/src/synth/elab-vhdl_context.adb @@ -53,6 +53,7 @@ package body Elab.Vhdl_Context is new Synth_Instance_Type'(Max_Objs => Global_Info.Nbr_Objects, Is_Const => False, Is_Error => False, + Flag1 | Flag2 => False, Id => Inst_Tables.Last + 1, Block_Scope => Global_Info, Up_Block => null, @@ -101,6 +102,7 @@ package body Elab.Vhdl_Context is Res := new Synth_Instance_Type'(Max_Objs => Nbr_Objs, Is_Const => False, Is_Error => False, + Flag1 | Flag2 => False, Id => Inst_Tables.Last + 1, Block_Scope => Scope, Up_Block => Parent, @@ -142,6 +144,7 @@ package body Elab.Vhdl_Context is Res := new Synth_Instance_Type'(Max_Objs => Object_Slot_Type (Len), Is_Const => False, Is_Error => False, + Flag1 | Flag2 => False, Id => Inst_Tables.Last + 1, Block_Scope => Info, Up_Block => Parent, @@ -237,6 +240,28 @@ package body Elab.Vhdl_Context is return Inst.Foreign; end Get_Instance_Foreign; + procedure Set_Indiv_Signal_Assoc_Flag (Inst : Synth_Instance_Acc) is + begin + Inst.Flag1 := True; + end Set_Indiv_Signal_Assoc_Flag; + + function Get_Indiv_Signal_Assoc_Flag (Inst : Synth_Instance_Acc) + return Boolean is + begin + return Inst.Flag1; + end Get_Indiv_Signal_Assoc_Flag; + + procedure Set_Indiv_Signal_Assoc_Parent_Flag (Inst : Synth_Instance_Acc) is + begin + Inst.Flag2 := True; + end Set_Indiv_Signal_Assoc_Parent_Flag; + + function Get_Indiv_Signal_Assoc_Parent_Flag (Inst : Synth_Instance_Acc) + return Boolean is + begin + return Inst.Flag2; + end Get_Indiv_Signal_Assoc_Parent_Flag; + procedure Add_Extra_Instance (Inst : Synth_Instance_Acc; Extra : Synth_Instance_Acc) is begin diff --git a/src/synth/elab-vhdl_context.ads b/src/synth/elab-vhdl_context.ads index 8598bbf56..76fd35473 100644 --- a/src/synth/elab-vhdl_context.ads +++ b/src/synth/elab-vhdl_context.ads @@ -74,6 +74,8 @@ package Elab.Vhdl_Context is procedure Set_Error (Inst : Synth_Instance_Acc); + -- Get/Set the const flag. + -- This is for subprograms, and set when all parameters are static. function Get_Instance_Const (Inst : Synth_Instance_Acc) return Boolean; procedure Set_Instance_Const (Inst : Synth_Instance_Acc; Val : Boolean); @@ -90,6 +92,19 @@ package Elab.Vhdl_Context is procedure Set_Instance_Foreign (Inst : Synth_Instance_Acc; N : Int32); function Get_Instance_Foreign (Inst : Synth_Instance_Acc) return Int32; + -- For simulation: set a flag if a signal parameter has individual + -- association. In that case, the value of the parameter must be + -- updated after a wait statement. + procedure Set_Indiv_Signal_Assoc_Flag (Inst : Synth_Instance_Acc); + function Get_Indiv_Signal_Assoc_Flag (Inst : Synth_Instance_Acc) + return Boolean; + + -- For simulation: set if a parent has the Indiv_Signal_Assoc_Flag set. + -- In that case, update must continue in the parent. + procedure Set_Indiv_Signal_Assoc_Parent_Flag (Inst : Synth_Instance_Acc); + function Get_Indiv_Signal_Assoc_Parent_Flag (Inst : Synth_Instance_Acc) + return Boolean; + -- Add/Get extra instances. -- Those instances are verification units. procedure Add_Extra_Instance (Inst : Synth_Instance_Acc; @@ -233,6 +248,13 @@ private -- of this instance. Is_Error : Boolean; + -- For simulation: set if a subprogram has a signal parameter + -- associated by individual elements. + Flag1 : Boolean; + + -- For simulation: set if a parent instance has Flag1 set. + Flag2 : Boolean; + Id : Instance_Id_Type; -- The corresponding info for this instance. diff --git a/src/synth/elab-vhdl_debug.adb b/src/synth/elab-vhdl_debug.adb index d47c310f0..e5e40011e 100644 --- a/src/synth/elab-vhdl_debug.adb +++ b/src/synth/elab-vhdl_debug.adb @@ -280,6 +280,8 @@ package body Elab.Vhdl_Debug is Disp_Memtyp (Get_Memtyp (Vt), Vtype); when Value_Dyn_Alias => Put ("dyn alias"); + when Value_Sig_Val => + Put ("sig val"); when Value_Memory => Disp_Memtyp (Get_Memtyp (Vt), Vtype); end case; diff --git a/src/synth/elab-vhdl_values-debug.adb b/src/synth/elab-vhdl_values-debug.adb index aec0b1e20..c995c0204 100644 --- a/src/synth/elab-vhdl_values-debug.adb +++ b/src/synth/elab-vhdl_values-debug.adb @@ -324,6 +324,9 @@ package body Elab.Vhdl_Values.Debug is when Value_Dyn_Alias => Put ("dyn alias: "); Debug_Typ1 (V.Typ); + when Value_Sig_Val => + Put ("sig val: "); + Debug_Typ1 (V.Typ); end case; end Debug_Valtyp; diff --git a/src/synth/elab-vhdl_values.adb b/src/synth/elab-vhdl_values.adb index 045fcce2e..deb0d0ccb 100644 --- a/src/synth/elab-vhdl_values.adb +++ b/src/synth/elab-vhdl_values.adb @@ -34,6 +34,7 @@ package body Elab.Vhdl_Values is | Value_Wire | Value_Signal | Value_Dyn_Alias + | Value_Sig_Val | Value_Quantity | Value_Terminal => return False; @@ -268,6 +269,26 @@ package body Elab.Vhdl_Values is end if; end Strip_Const; + function Create_Value_Sig_Val (Sigs : Memory_Ptr; + Vals : Memory_Ptr; + Pool : Areapool_Acc) return Value_Acc + is + subtype Value_Type_Sig_Val is Value_Type (Value_Sig_Val); + function Alloc is new Areapools.Alloc_On_Pool_Addr (Value_Type_Sig_Val); + begin + return To_Value_Acc (Alloc (Pool, (Kind => Value_Sig_Val, + I_Sigs => Sigs, + I_Vals => Vals))); + end Create_Value_Sig_Val; + + function Create_Value_Sig_Val (Sigs : Memory_Ptr; + Vals : Memory_Ptr; + Typ : Type_Acc; + Pool : Areapool_Acc) return Valtyp is + begin + return (Typ, Create_Value_Sig_Val (Sigs, Vals, Pool)); + end Create_Value_Sig_Val; + procedure Write_Value (Dest : Memory_Ptr; Vt : Valtyp) is Mt : Memtyp; @@ -315,6 +336,8 @@ package body Elab.Vhdl_Values is Src.Val.D_Poff, Src.Val.D_Ptyp, Src.Val.D_Voff, Src.Val.D_Eoff, Current_Pool)); + when Value_Sig_Val => + raise Internal_Error; end case; return Res; end Copy; @@ -545,7 +568,8 @@ package body Elab.Vhdl_Values is when Value_Net | Value_Wire | Value_Signal - | Value_Dyn_Alias => + | Value_Dyn_Alias + | Value_Sig_Val => raise Internal_Error; when Value_Memory => return (V.Typ, V.Val.Mem); diff --git a/src/synth/elab-vhdl_values.ads b/src/synth/elab-vhdl_values.ads index 4ed86da22..0e72fd128 100644 --- a/src/synth/elab-vhdl_values.ads +++ b/src/synth/elab-vhdl_values.ads @@ -60,7 +60,10 @@ package Elab.Vhdl_Values is Value_Alias, -- Used only for associations. - Value_Dyn_Alias + Value_Dyn_Alias, + + -- Used only for individual signal associations in simulation + Value_Sig_Val ); type Value_Type (Kind : Value_Kind); @@ -114,6 +117,9 @@ package Elab.Vhdl_Values is D_Ptyp : Type_Acc; -- Type of the prefix (after offset). D_Voff : Uns32; -- Variable offset D_Eoff : Uns32; -- Fixed offset. + when Value_Sig_Val => + I_Sigs : Memory_Ptr; + I_Vals : Memory_Ptr; end case; end record; @@ -187,6 +193,11 @@ package Elab.Vhdl_Values is function Create_Value_Const (Val : Valtyp; Loc : Node; Pool : Areapool_Acc) return Valtyp; + function Create_Value_Sig_Val (Sigs : Memory_Ptr; + Vals : Memory_Ptr; + Typ : Type_Acc; + Pool : Areapool_Acc) return Valtyp; + -- If VAL is a const, replace it by its value. procedure Strip_Const (Vt : in out Valtyp); diff --git a/src/synth/synth-vhdl_context.adb b/src/synth/synth-vhdl_context.adb index 81143bea9..7d05e203a 100644 --- a/src/synth/synth-vhdl_context.adb +++ b/src/synth/synth-vhdl_context.adb @@ -464,7 +464,8 @@ package body Synth.Vhdl_Context is return True; when Value_Net | Value_Signal - | Value_Dyn_Alias => + | Value_Dyn_Alias + | Value_Sig_Val => return False; when Value_Quantity | Value_Terminal => diff --git a/src/synth/synth-vhdl_expr.adb b/src/synth/synth-vhdl_expr.adb index 036e5a27e..83aecb420 100644 --- a/src/synth/synth-vhdl_expr.adb +++ b/src/synth/synth-vhdl_expr.adb @@ -2060,6 +2060,7 @@ package body Synth.Vhdl_Expr is Res := Synth_Name (Syn_Inst, Expr); if Res.Val /= null then if (Res.Val.Kind = Value_Signal + or else Res.Val.Kind = Value_Sig_Val or else (Res.Val.Kind = Value_Alias and then Res.Val.A_Obj.Kind = Value_Signal)) then diff --git a/src/synth/synth-vhdl_insts.adb b/src/synth/synth-vhdl_insts.adb index fc9788f78..88f023354 100644 --- a/src/synth/synth-vhdl_insts.adb +++ b/src/synth/synth-vhdl_insts.adb @@ -230,7 +230,8 @@ package body Synth.Vhdl_Insts is | Value_File | Value_Quantity | Value_Terminal - | Value_Dyn_Alias => + | Value_Dyn_Alias + | Value_Sig_Val => raise Internal_Error; end case; end Hash_Const; diff --git a/src/synth/synth-vhdl_stmts.adb b/src/synth/synth-vhdl_stmts.adb index c010ced3e..bba8c823b 100644 --- a/src/synth/synth-vhdl_stmts.adb +++ b/src/synth/synth-vhdl_stmts.adb @@ -770,7 +770,8 @@ package body Synth.Vhdl_Stmts is | Value_Const | Value_Alias | Value_Dyn_Alias - | Value_Signal => + | Value_Signal + | Value_Sig_Val => raise Internal_Error; end case; when Target_Aggregate => @@ -2031,17 +2032,6 @@ package body Synth.Vhdl_Stmts is return Count; end Count_Individual_Associations; - type Assoc_Record is record - Formal : Node; - Form_Off : Value_Offsets; - - Act_Base : Valtyp; - Act_Typ : Type_Acc; - Act_Off : Value_Offsets; - Act_Dyn : Dyn_Name; - end record; - - type Assoc_Array is array (Natural range <>) of Assoc_Record; type Assoc_Array_Acc is access Assoc_Array; procedure Free_Assoc_Array is new Ada.Unchecked_Deallocation (Assoc_Array, Assoc_Array_Acc); @@ -2145,18 +2135,24 @@ package body Synth.Vhdl_Stmts is A.Act_Typ.Sz); end; end loop; - declare - D : Destroy_Type; - begin - Destroy_Init (D, Subprg_Inst); - Destroy_Object (D, Inter); - Destroy_Finish (D); - end; + elsif Flags.Flag_Simulation then + Res := Hook_Create_Value_For_Signal_Individual_Assocs + (Subprg_Inst, Assocs.all, Formal_Typ); else Res := No_Valtyp; raise Internal_Error; end if; + -- Destroy the object. It will be recreated by + -- Synth_Subprogram_Association. + declare + D : Destroy_Type; + begin + Destroy_Init (D, Subprg_Inst); + Destroy_Object (D, Inter); + Destroy_Finish (D); + end; + Free_Assoc_Array (Assocs); return Res; diff --git a/src/synth/synth-vhdl_stmts.ads b/src/synth/synth-vhdl_stmts.ads index c07dc7224..ac9cd13d8 100644 --- a/src/synth/synth-vhdl_stmts.ads +++ b/src/synth/synth-vhdl_stmts.ads @@ -211,6 +211,25 @@ package Synth.Vhdl_Stmts is Val : Valtyp; Loc : Node); + type Assoc_Record is record + Formal : Node; + Form_Off : Value_Offsets; + + Act_Base : Valtyp; + Act_Typ : Type_Acc; + Act_Off : Value_Offsets; + Act_Dyn : Dyn_Name; + end record; + + type Assoc_Array is array (Natural range <>) of Assoc_Record; + + -- For simulation: create a value for individual signal associations. + type Create_Value_For_Signal_Individual_Assocs_Acc is + access function (Inst : Synth_Instance_Acc; + Assocs : Assoc_Array; + Typ : Type_Acc) return Valtyp; + Hook_Create_Value_For_Signal_Individual_Assocs : + Create_Value_For_Signal_Individual_Assocs_Acc; private -- There are 2 execution mode: |