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authorTristan Gingold <tgingold@free.fr>2021-11-01 19:50:19 +0100
committerTristan Gingold <tgingold@free.fr>2021-11-01 21:11:10 +0100
commit86fd1ab3079b50c5b7234db2cedf3d1e8c0f081b (patch)
treee34bdcf719bdc08cb22a65e04ad67b57b0c06879 /src/synth/synth-vhdl_environment.ads
parent74043fa1aa40c375c7f299e6b5f1b6ea9150580e (diff)
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synth: do full elaboration before synthesis
Diffstat (limited to 'src/synth/synth-vhdl_environment.ads')
-rw-r--r--src/synth/synth-vhdl_environment.ads6
1 files changed, 3 insertions, 3 deletions
diff --git a/src/synth/synth-vhdl_environment.ads b/src/synth/synth-vhdl_environment.ads
index e9bf6129f..1a65b2a07 100644
--- a/src/synth/synth-vhdl_environment.ads
+++ b/src/synth/synth-vhdl_environment.ads
@@ -23,10 +23,10 @@ with Netlists.Builders;
with Vhdl.Nodes;
+with Elab.Vhdl_Objtypes; use Elab.Vhdl_Objtypes;
+
with Synth.Environment;
with Synth.Environment.Debug;
-with Synth.Objtypes; use Synth.Objtypes;
--- with Synth_Vhdl.Context;
package Synth.Vhdl_Environment is
@@ -52,7 +52,7 @@ package Synth.Vhdl_Environment is
package Env is new Synth.Environment
(Decl_Type => Decl_Type,
- Static_Type => Standard.Synth.Objtypes.Memtyp,
+ Static_Type => Elab.Vhdl_Objtypes.Memtyp,
Get_Width => Get_Bitwidth,
Is_Equal => Is_Equal,
Static_To_Net => Memtyp_To_Net,