From 86fd1ab3079b50c5b7234db2cedf3d1e8c0f081b Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Mon, 1 Nov 2021 19:50:19 +0100 Subject: synth: do full elaboration before synthesis --- src/synth/synth-vhdl_environment.ads | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'src/synth/synth-vhdl_environment.ads') diff --git a/src/synth/synth-vhdl_environment.ads b/src/synth/synth-vhdl_environment.ads index e9bf6129f..1a65b2a07 100644 --- a/src/synth/synth-vhdl_environment.ads +++ b/src/synth/synth-vhdl_environment.ads @@ -23,10 +23,10 @@ with Netlists.Builders; with Vhdl.Nodes; +with Elab.Vhdl_Objtypes; use Elab.Vhdl_Objtypes; + with Synth.Environment; with Synth.Environment.Debug; -with Synth.Objtypes; use Synth.Objtypes; --- with Synth_Vhdl.Context; package Synth.Vhdl_Environment is @@ -52,7 +52,7 @@ package Synth.Vhdl_Environment is package Env is new Synth.Environment (Decl_Type => Decl_Type, - Static_Type => Standard.Synth.Objtypes.Memtyp, + Static_Type => Elab.Vhdl_Objtypes.Memtyp, Get_Width => Get_Bitwidth, Is_Equal => Is_Equal, Static_To_Net => Memtyp_To_Net, -- cgit v1.2.3