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author | Tristan Gingold <tgingold@free.fr> | 2022-05-22 09:09:14 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2022-05-22 09:09:14 +0200 |
commit | 946320e0984df406f0e3c50cd3db0fb49df5ec9b (patch) | |
tree | 97d51eff8e649cacf5ad081f7dd9258553ddb2b2 /src/synth/synth-vhdl_environment.adb | |
parent | c56080fed0b46083cf138962c5bb125ea08bfa0e (diff) | |
download | ghdl-946320e0984df406f0e3c50cd3db0fb49df5ec9b.tar.gz ghdl-946320e0984df406f0e3c50cd3db0fb49df5ec9b.tar.bz2 ghdl-946320e0984df406f0e3c50cd3db0fb49df5ec9b.zip |
synth: merge value for type_vector and type_array
Diffstat (limited to 'src/synth/synth-vhdl_environment.adb')
-rw-r--r-- | src/synth/synth-vhdl_environment.adb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/synth/synth-vhdl_environment.adb b/src/synth/synth-vhdl_environment.adb index c7f7daccc..711673fda 100644 --- a/src/synth/synth-vhdl_environment.adb +++ b/src/synth/synth-vhdl_environment.adb @@ -124,7 +124,7 @@ package body Synth.Vhdl_Environment is Info_Msg_Synth (+Loc, " " & Prefix - & "(" & Info_Subrange_Vhdl (Off, Wd, Typ.Vbound) & ")"); + & "(" & Info_Subrange_Vhdl (Off, Wd, Typ.Abound) & ")"); end if; when Type_Slice | Type_Array => |