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author | Tristan Gingold <tgingold@free.fr> | 2019-07-25 08:06:50 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-07-25 08:06:50 +0200 |
commit | 16b564158369b435372de417e2c0ce8e71af6419 (patch) | |
tree | 10334f70b3d214f161ad31d48f26f361d2def501 /src/synth/synth-insts.adb | |
parent | 6e1f2bbd6eabc81206b136d749182426196bb6d9 (diff) | |
download | ghdl-16b564158369b435372de417e2c0ce8e71af6419.tar.gz ghdl-16b564158369b435372de417e2c0ce8e71af6419.tar.bz2 ghdl-16b564158369b435372de417e2c0ce8e71af6419.zip |
synth: handle bit.
Diffstat (limited to 'src/synth/synth-insts.adb')
-rw-r--r-- | src/synth/synth-insts.adb | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/src/synth/synth-insts.adb b/src/synth/synth-insts.adb index 7c178b4f4..6aa0e78ad 100644 --- a/src/synth/synth-insts.adb +++ b/src/synth/synth-insts.adb @@ -420,14 +420,19 @@ package body Synth.Insts is procedure Create_Component_Wire (Inter : Node; Val : Value_Acc) is Value : Net; + W : Width; begin case Val.Kind is when Value_Wire => -- Create a gate for the output, so that it could be read. Val.W := Alloc_Wire (Wire_Output, Inter); + if Val.W_Bound = null then + W := 1; + else + W := Val.W_Bound.Len; + end if; Value := Builders.Build_Signal - (Build_Context, New_Sname (No_Sname, Get_Identifier (Inter)), - Val.W_Bound.Len); + (Build_Context, New_Sname (No_Sname, Get_Identifier (Inter)), W); Set_Wire_Gate (Val.W, Value); when others => raise Internal_Error; @@ -676,7 +681,8 @@ package body Synth.Insts is -- Create a gate for the output, so that it could be read. Val.W := Alloc_Wire (Wire_Output, Inter); W := Get_Output_Desc (Get_Module (Self_Inst), Idx).W; - pragma Assert (W = Val.W_Bound.Len); + pragma Assert ((W = 1 and then Val.W_Bound = null) + or else (W /= 1 and then W = Val.W_Bound.Len)); Value := Builders.Build_Output (Build_Context, W); Set_Location (Value, Inter); Inp := Get_Input (Self_Inst, Idx); |