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| author | Tristan Gingold <tgingold@free.fr> | 2019-08-07 06:22:59 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-08-08 04:33:32 +0200 |
| commit | afafa2c3f856df075db309d553988ff5407c56ff (patch) | |
| tree | af74fe1f2cc750d742f3e3b61f0288726454fc96 /src/synth/synth-expr.adb | |
| parent | 97d3a89195c8aeb981a7f4171b939c48ec4bdfaa (diff) | |
| download | ghdl-afafa2c3f856df075db309d553988ff5407c56ff.tar.gz ghdl-afafa2c3f856df075db309d553988ff5407c56ff.tar.bz2 ghdl-afafa2c3f856df075db309d553988ff5407c56ff.zip | |
synth: handle 1 bit integer in disp_vhdl, fix range in synth-expr.
Diffstat (limited to 'src/synth/synth-expr.adb')
| -rw-r--r-- | src/synth/synth-expr.adb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/synth/synth-expr.adb b/src/synth/synth-expr.adb index c3f1f2589..dab693362 100644 --- a/src/synth/synth-expr.adb +++ b/src/synth/synth-expr.adb @@ -460,7 +460,7 @@ package body Synth.Expr is elsif Lo >= 0 then -- Positive. V.Is_Signed := False; - V.W := Width (Clog2 (Uns64 (Hi))); + V.W := Width (Clog2 (Uns64 (Hi) + 1)); elsif Lo = Int64'First then -- Handle possible overflow. V.Is_Signed := True; |