diff options
| author | Tristan Gingold <tgingold@free.fr> | 2019-07-04 18:22:21 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-07-04 18:22:21 +0200 |
| commit | 457ab6ebd8b17685c79047ad6d50e1b26665c5c3 (patch) | |
| tree | 894cd30ab8ecdf774bd181021bf17151f62e2af2 | |
| parent | 9b70a1f0bf970706a62dc14e382c91f3616ab51c (diff) | |
| download | ghdl-457ab6ebd8b17685c79047ad6d50e1b26665c5c3.tar.gz ghdl-457ab6ebd8b17685c79047ad6d50e1b26665c5c3.tar.bz2 ghdl-457ab6ebd8b17685c79047ad6d50e1b26665c5c3.zip | |
synth: handle some "/=".
| -rw-r--r-- | src/synth/synth-expr.adb | 3 | ||||
| -rw-r--r-- | src/vhdl/vhdl-ieee-numeric.adb | 20 |
2 files changed, 23 insertions, 0 deletions
diff --git a/src/synth/synth-expr.adb b/src/synth/synth-expr.adb index 23d97a129..ecdb99cb0 100644 --- a/src/synth/synth-expr.adb +++ b/src/synth/synth-expr.adb @@ -751,6 +751,9 @@ package body Synth.Expr is | Iir_Predefined_Ieee_Std_Logic_Unsigned_Eq_Slv_Slv => -- "=" (Unsigned, Unsigned) [resize] return Synth_Compare_Uns_Uns (Id_Eq); + when Iir_Predefined_Ieee_Numeric_Std_Ne_Uns_Nat => + -- "/=" (Unsigned, Natural) + return Synth_Compare_Uns_Nat (Id_Ne); when Iir_Predefined_Ieee_Numeric_Std_Lt_Uns_Nat => -- "<" (Unsigned, Natural) if Is_Const (Right) and then Right.Scal = 0 then diff --git a/src/vhdl/vhdl-ieee-numeric.adb b/src/vhdl/vhdl-ieee-numeric.adb index 2abb92940..24958e08a 100644 --- a/src/vhdl/vhdl-ieee-numeric.adb +++ b/src/vhdl/vhdl-ieee-numeric.adb @@ -91,6 +91,24 @@ package body Vhdl.Ieee.Numeric is (others => (others => Iir_Predefined_None))); + Ne_Patterns : constant Binary_Pattern_Type := + (Pkg_Std => + (Type_Unsigned => + (Arg_Vect_Vect => Iir_Predefined_Ieee_Numeric_Std_Ne_Uns_Uns, + Arg_Vect_Scal => Iir_Predefined_Ieee_Numeric_Std_Ne_Uns_Nat, + Arg_Scal_Vect => Iir_Predefined_Ieee_Numeric_Std_Ne_Nat_Uns, + Arg_Vect_Log => Iir_Predefined_None, + Arg_Log_Vect => Iir_Predefined_None), + Type_Signed => + (Arg_Vect_Vect => Iir_Predefined_Ieee_Numeric_Std_Ne_Sgn_Sgn, + Arg_Vect_Scal => Iir_Predefined_Ieee_Numeric_Std_Ne_Sgn_Int, + Arg_Scal_Vect => Iir_Predefined_Ieee_Numeric_Std_Ne_Int_Sgn, + Arg_Vect_Log => Iir_Predefined_None, + Arg_Log_Vect => Iir_Predefined_None)), + Pkg_Bit => + (others => + (others => Iir_Predefined_None))); + Lt_Patterns : constant Binary_Pattern_Type := (Pkg_Std => (Type_Unsigned => @@ -323,6 +341,8 @@ package body Vhdl.Ieee.Numeric is Handle_Binary (Sub_Patterns); when Name_Op_Equality => Handle_Binary (Eq_Patterns); + when Name_Op_Inequality => + Handle_Binary (Ne_Patterns); when Name_Op_Less => Handle_Binary (Lt_Patterns); when Name_To_Bstring |