netlists: add memidx1 and memidx2 gates.

4 files changed, 101 insertions, 8 deletions

diff --git a/src/synth/ghdlsynth_gates.h b/src/synth/ghdlsynth_gates.h
index 3f1afd44d..f8310ec9c 100644
--- a/src/synth/ghdlsynth_gates.h
+++ b/src/synth/ghdlsynth_gates.h
@@ -61,10 +61,12 @@ enum Module_Id {
    Id_Extract = 68,
    Id_Dyn_Extract = 69,
    Id_Dyn_Insert = 70,
-   Id_Edge = 71,
-   Id_Assert = 72,
-   Id_Assume = 73,
-   Id_Cover = 74,
+   Id_Memidx1 = 71,
+   Id_Memidx2 = 72,
+   Id_Edge = 80,
+   Id_Assert = 81,
+   Id_Assume = 82,
+   Id_Cover = 83,
    Id_Const_UB32 = 96,
    Id_Const_SB32 = 97,
    Id_Const_UL32 = 98,
diff --git a/src/synth/netlists-builders.adb b/src/synth/netlists-builders.adb
index 7d885a9f6..12aee039d 100644
--- a/src/synth/netlists-builders.adb
+++ b/src/synth/netlists-builders.adb
@@ -250,6 +250,40 @@ package body Netlists.Builders is
                      Typ => Param_Uns32)));
    end Create_Dyn_Insert_Module;
 
+   procedure Create_Memidx_Module (Ctxt : Context_Acc)
+   is
+      Outputs : Port_Desc_Array (0 .. 0);
+      Inputs : Port_Desc_Array (0 .. 1);
+      Res : Module;
+   begin
+      Res := New_User_Module
+        (Ctxt.Design, New_Sname_Artificial (Get_Identifier ("memidx1")),
+         Id_Memidx1, 1, 1, 2);
+      Ctxt.M_Memidx1 := Res;
+      Outputs := (0 => Create_Output ("o"));
+      Inputs (0) := Create_Input ("i");
+      Set_Port_Desc (Res, Inputs (0 .. 0), Outputs);
+      Set_Param_Desc
+        (Res, (0 => (New_Sname_Artificial (Get_Identifier ("step")),
+                     Typ => Param_Uns32),
+               1 => (New_Sname_Artificial (Get_Identifier ("max")),
+                     Typ => Param_Uns32)));
+
+      Res := New_User_Module
+        (Ctxt.Design, New_Sname_Artificial (Get_Identifier ("memidx2")),
+         Id_Memidx2, 2, 1, 2);
+      Ctxt.M_Memidx2 := Res;
+      Outputs := (0 => Create_Output ("o"));
+      Inputs := (0 => Create_Input ("i"),
+                 1 => Create_Input ("add"));
+      Set_Port_Desc (Res, Inputs, Outputs);
+      Set_Param_Desc
+        (Res, (0 => (New_Sname_Artificial (Get_Identifier ("step")),
+                     Typ => Param_Uns32),
+               1 => (New_Sname_Artificial (Get_Identifier ("max")),
+                     Typ => Param_Uns32)));
+   end Create_Memidx_Module;
+
    procedure Create_Edge_Module (Ctxt : Context_Acc;
                                  Res : out Module;
                                  Name : Name_Id)
@@ -481,6 +515,7 @@ package body Netlists.Builders is
       Create_Extract_Module (Res);
       Create_Dyn_Extract_Module (Res);
       Create_Dyn_Insert_Module (Res);
+      Create_Memidx_Module (Res);
 
       Create_Monadic_Module (Design, Res.M_Truncate (Id_Utrunc),
                              Get_Identifier ("utrunc"), Id_Utrunc);
@@ -946,6 +981,48 @@ package body Netlists.Builders is
       return O;
    end Build_Dyn_Insert;
 
+   function Build_Memidx1
+     (Ctxt : Context_Acc; I : Net; Step : Uns32; Max : Uns32) return Net
+   is
+      W : constant Width := Get_Width (I);
+      pragma Assert (W /= No_Width);
+      pragma Assert (Step > 0);
+      pragma Assert (W > 0);
+      Inst : Instance;
+      O : Net;
+   begin
+      Inst := New_Internal_Instance (Ctxt, Ctxt.M_Memidx1);
+      O := Get_Output (Inst, 0);
+      Set_Width (O, W);
+      Connect (Get_Input (Inst, 0), I);
+      Set_Param_Uns32 (Inst, 0, Step);
+      Set_Param_Uns32 (Inst, 1, Max);
+      return O;
+   end Build_Memidx1;
+
+   function Build_Memidx2
+     (Ctxt : Context_Acc; I : Net; Add : Net; Step : Uns32; Max : Uns32)
+     return Net
+   is
+      W : constant Width := Get_Width (I);
+      pragma Assert (W /= No_Width);
+      pragma Assert (Get_Width (Add) = W);
+      pragma Assert (Get_Width (Add) /= No_Width);
+      pragma Assert (Step > 0);
+      pragma Assert (W > 0);
+      Inst : Instance;
+      O : Net;
+   begin
+      Inst := New_Internal_Instance (Ctxt, Ctxt.M_Memidx2);
+      O := Get_Output (Inst, 0);
+      Set_Width (O, W);
+      Connect (Get_Input (Inst, 0), I);
+      Connect (Get_Input (Inst, 1), Add);
+      Set_Param_Uns32 (Inst, 0, Step);
+      Set_Param_Uns32 (Inst, 1, Max);
+      return O;
+   end Build_Memidx2;
+
    function Build_Object (Ctxt : Context_Acc; M : Module; W : Width) return Net
    is
       Inst : Instance;
diff --git a/src/synth/netlists-builders.ads b/src/synth/netlists-builders.ads
index 5a658c14f..a00014168 100644
--- a/src/synth/netlists-builders.ads
+++ b/src/synth/netlists-builders.ads
@@ -136,6 +136,12 @@ package Netlists.Builders is
      (Ctxt : Context_Acc; I : Net; V : Net; P : Net; Step : Uns32; Off : Uns32)
      return Net;
 
+   function Build_Memidx1
+     (Ctxt : Context_Acc; I : Net; Step : Uns32; Max : Uns32) return Net;
+   function Build_Memidx2
+     (Ctxt : Context_Acc; I : Net; Add : Net; Step : Uns32; Max : Uns32)
+     return Net;
+
    function Build_Output (Ctxt : Context_Acc; W : Width) return Net;
    function Build_Signal (Ctxt : Context_Acc; Name : Sname; W : Width)
                          return Net;
@@ -204,6 +210,8 @@ private
       M_Extract : Module;
       M_Dyn_Extract : Module;
       M_Dyn_Insert : Module;
+      M_Memidx1 : Module;
+      M_Memidx2 : Module;
       M_Assert : Module;
       M_Assume : Module;
       M_Cover : Module;
diff --git a/src/synth/netlists-gates.ads b/src/synth/netlists-gates.ads
index 1379c038d..41cb597f6 100644
--- a/src/synth/netlists-gates.ads
+++ b/src/synth/netlists-gates.ads
@@ -153,15 +153,21 @@ package Netlists.Gates is
    --  OUT := T
    Id_Dyn_Insert : constant Module_Id := 70;
 
+   --  OUT := IN0 * STEP,  IN0 < MAX
+   Id_Memidx1 : constant Module_Id := 71;
+
+   --  OUT := IN0 * STEP + IN1,  IN0 < MAX
+   Id_Memidx2 : constant Module_Id := 72;
+
    --  Positive/rising edge detector.  This is a pseudo gate.
    --  A negative edge detector can be made using by negating the clock before
    --  the detector.
-   Id_Edge : constant Module_Id := 71;
+   Id_Edge : constant Module_Id := 80;
 
    --  Input signal must always be true.
-   Id_Assert : constant Module_Id := 72;
-   Id_Assume : constant Module_Id := 73;
-   Id_Cover : constant Module_Id := 74;
+   Id_Assert : constant Module_Id := 81;
+   Id_Assume : constant Module_Id := 82;
+   Id_Cover : constant Module_Id := 83;
 
    --  Constants are gates with only one constant output.  There are multiple
    --  kind of constant gates: for small width, the value is stored as a