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author | Tristan Gingold <tgingold@free.fr> | 2020-01-20 07:55:19 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-01-20 07:55:19 +0100 |
commit | ac830367cc0c979472cabb9173102d591817f98c (patch) | |
tree | 832d96741dfb5e075f105ef25db3b17a29674fea /src/synth/netlists-disp_vhdl.adb | |
parent | 5ea993bae3c78ee8bdda3942be80fa38091f4591 (diff) | |
download | ghdl-ac830367cc0c979472cabb9173102d591817f98c.tar.gz ghdl-ac830367cc0c979472cabb9173102d591817f98c.tar.bz2 ghdl-ac830367cc0c979472cabb9173102d591817f98c.zip |
synth: add id_abs gate. For #1101
Diffstat (limited to 'src/synth/netlists-disp_vhdl.adb')
-rw-r--r-- | src/synth/netlists-disp_vhdl.adb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb index 2bf9005cf..398e29a16 100644 --- a/src/synth/netlists-disp_vhdl.adb +++ b/src/synth/netlists-disp_vhdl.adb @@ -760,6 +760,8 @@ package body Netlists.Disp_Vhdl is Disp_Template (" \o0 <= not \i0;" & NL, Inst); when Id_Neg => Disp_Template (" \o0 <= std_logic_vector(-\si0);" & NL, Inst); + when Id_Abs=> + Disp_Template (" \o0 <= std_logic_vector(abs \si0);" & NL, Inst); when Id_Extract => Disp_Template (" \o0 <= ", Inst); Disp_Extract (Inst); |