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author | Tristan Gingold <tgingold@free.fr> | 2020-01-20 07:55:19 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-01-20 07:55:19 +0100 |
commit | ac830367cc0c979472cabb9173102d591817f98c (patch) | |
tree | 832d96741dfb5e075f105ef25db3b17a29674fea /src | |
parent | 5ea993bae3c78ee8bdda3942be80fa38091f4591 (diff) | |
download | ghdl-ac830367cc0c979472cabb9173102d591817f98c.tar.gz ghdl-ac830367cc0c979472cabb9173102d591817f98c.tar.bz2 ghdl-ac830367cc0c979472cabb9173102d591817f98c.zip |
synth: add id_abs gate. For #1101
Diffstat (limited to 'src')
-rw-r--r-- | src/synth/ghdlsynth_gates.h | 15 | ||||
-rw-r--r-- | src/synth/netlists-builders.adb | 1 | ||||
-rw-r--r-- | src/synth/netlists-disp_vhdl.adb | 2 | ||||
-rw-r--r-- | src/synth/netlists-gates.ads | 21 | ||||
-rw-r--r-- | src/synth/synth-oper.adb | 2 | ||||
-rw-r--r-- | src/synth/synth-static_oper.adb | 2 | ||||
-rw-r--r-- | src/vhdl/vhdl-ieee-numeric.adb | 9 | ||||
-rw-r--r-- | src/vhdl/vhdl-nodes.ads | 2 |
8 files changed, 37 insertions, 17 deletions
diff --git a/src/synth/ghdlsynth_gates.h b/src/synth/ghdlsynth_gates.h index 6530f300b..b215f9793 100644 --- a/src/synth/ghdlsynth_gates.h +++ b/src/synth/ghdlsynth_gates.h @@ -21,13 +21,14 @@ enum Module_Id { Id_Umod = 15, Id_Smod = 16, Id_Srem = 17, - Id_Lsl = 20, - Id_Lsr = 21, - Id_Asr = 22, - Id_Rol = 23, - Id_Ror = 24, - Id_Not = 25, - Id_Neg = 26, + Id_Not = 18, + Id_Neg = 19, + Id_Abs = 20, + Id_Lsl = 22, + Id_Lsr = 23, + Id_Asr = 24, + Id_Rol = 25, + Id_Ror = 26, Id_Eq = 27, Id_Ne = 28, Id_Ule = 29, diff --git a/src/synth/netlists-builders.adb b/src/synth/netlists-builders.adb index 9db99a20e..d869ebeba 100644 --- a/src/synth/netlists-builders.adb +++ b/src/synth/netlists-builders.adb @@ -597,6 +597,7 @@ package body Netlists.Builders is Create_Monadic_Module (Design, Res.M_Monadic (Id_Not), Name_Not, Id_Not); Create_Monadic_Module (Design, Res.M_Monadic (Id_Neg), Get_Identifier ("neg"), Id_Neg); + Create_Monadic_Module (Design, Res.M_Monadic (Id_Abs), Name_Abs, Id_Abs); Create_Compare_Module (Design, Res.M_Compare (Id_Eq), Get_Identifier ("eq"), Id_Eq); diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb index 2bf9005cf..398e29a16 100644 --- a/src/synth/netlists-disp_vhdl.adb +++ b/src/synth/netlists-disp_vhdl.adb @@ -760,6 +760,8 @@ package body Netlists.Disp_Vhdl is Disp_Template (" \o0 <= not \i0;" & NL, Inst); when Id_Neg => Disp_Template (" \o0 <= std_logic_vector(-\si0);" & NL, Inst); + when Id_Abs=> + Disp_Template (" \o0 <= std_logic_vector(abs \si0);" & NL, Inst); when Id_Extract => Disp_Template (" \o0 <= ", Inst); Disp_Extract (Inst); diff --git a/src/synth/netlists-gates.ads b/src/synth/netlists-gates.ads index e185ee085..bb5e64204 100644 --- a/src/synth/netlists-gates.ads +++ b/src/synth/netlists-gates.ads @@ -43,28 +43,29 @@ package Netlists.Gates is subtype Dyadic_Module_Id is Module_Id range Id_And .. Id_Srem; + Id_Not : constant Module_Id := 18; + Id_Neg : constant Module_Id := 19; + Id_Abs : constant Module_Id := 20; + + subtype Monadic_Module_Id is Module_Id range Id_Not .. Id_Abs; + -- Logical and arithmetic shifts. -- FIXME: clarify right operand: width, large values - Id_Lsl : constant Module_Id := 20; - Id_Lsr : constant Module_Id := 21; - Id_Asr : constant Module_Id := 22; + Id_Lsl : constant Module_Id := 22; + Id_Lsr : constant Module_Id := 23; + Id_Asr : constant Module_Id := 24; subtype Shift_Module_Id is Module_Id range Id_Lsl .. Id_Asr; -- Rotations. -- FIXME: clarify right operand. - Id_Rol : constant Module_Id := 23; - Id_Ror : constant Module_Id := 24; + Id_Rol : constant Module_Id := 25; + Id_Ror : constant Module_Id := 26; subtype Rotate_Module_Id is Module_Id range Id_Lsl .. Id_Asr; subtype Shift_Rotate_Module_Id is Module_Id range Id_Lsl .. Id_Ror; - Id_Not : constant Module_Id := 25; - Id_Neg : constant Module_Id := 26; - - subtype Monadic_Module_Id is Module_Id range Id_Not .. Id_Neg; - Id_Eq : constant Module_Id := 27; Id_Ne : constant Module_Id := 28; Id_Ule : constant Module_Id := 29; diff --git a/src/synth/synth-oper.adb b/src/synth/synth-oper.adb index a5dc07679..8f1a48011 100644 --- a/src/synth/synth-oper.adb +++ b/src/synth/synth-oper.adb @@ -929,6 +929,8 @@ package body Synth.Oper is when Iir_Predefined_Ieee_Numeric_Std_Neg_Uns | Iir_Predefined_Ieee_Numeric_Std_Neg_Sgn => return Synth_Vec_Monadic (Id_Neg); + when Iir_Predefined_Ieee_Numeric_Std_Abs_Sgn => + return Synth_Vec_Monadic (Id_Abs); when Iir_Predefined_Ieee_1164_Vector_And_Reduce => return Synth_Vec_Reduce_Monadic(Id_Red_And); when Iir_Predefined_Ieee_1164_Vector_Or_Reduce => diff --git a/src/synth/synth-static_oper.adb b/src/synth/synth-static_oper.adb index e366aefb9..c756bd3b0 100644 --- a/src/synth/synth-static_oper.adb +++ b/src/synth/synth-static_oper.adb @@ -514,6 +514,8 @@ package body Synth.Static_Oper is when Iir_Predefined_Integer_Negation => return Create_Value_Discrete (-Operand.Scal, Oper_Typ); + when Iir_Predefined_Integer_Absolute => + return Create_Value_Discrete (abs Operand.Scal, Oper_Typ); when Iir_Predefined_Floating_Negation => return Create_Value_Float (-Operand.Fp, Oper_Typ); diff --git a/src/vhdl/vhdl-ieee-numeric.adb b/src/vhdl/vhdl-ieee-numeric.adb index 9b93ffacc..10aa92d53 100644 --- a/src/vhdl/vhdl-ieee-numeric.adb +++ b/src/vhdl/vhdl-ieee-numeric.adb @@ -227,6 +227,13 @@ package body Vhdl.Ieee.Numeric is Pkg_Bit => (others => Iir_Predefined_None)); + Abs_Patterns : constant Unary_Pattern_Type := + (Pkg_Std => + (Type_Unsigned => Iir_Predefined_None, + Type_Signed => Iir_Predefined_Ieee_Numeric_Std_Abs_Sgn), + Pkg_Bit => + (others => Iir_Predefined_None)); + Not_Patterns : constant Unary_Pattern_Type := (Pkg_Std => (Type_Unsigned => Iir_Predefined_Ieee_Numeric_Std_Not_Uns, @@ -688,6 +695,8 @@ package body Vhdl.Ieee.Numeric is Handle_Unary (Neg_Patterns); when Name_Not => Handle_Unary (Not_Patterns); + when Name_Abs => + Handle_Unary (Abs_Patterns); when Name_To_Integer => Handle_To_Integer; when others => diff --git a/src/vhdl/vhdl-nodes.ads b/src/vhdl/vhdl-nodes.ads index 0f9a4c213..1305632d7 100644 --- a/src/vhdl/vhdl-nodes.ads +++ b/src/vhdl/vhdl-nodes.ads @@ -5575,6 +5575,8 @@ package Vhdl.Nodes is Iir_Predefined_Ieee_Numeric_Std_Not_Uns, Iir_Predefined_Ieee_Numeric_Std_Not_Sgn, + Iir_Predefined_Ieee_Numeric_Std_Abs_Sgn, + Iir_Predefined_Ieee_Numeric_Std_And_Uns_Uns, Iir_Predefined_Ieee_Numeric_Std_And_Sgn_Sgn, |