From 134c6ed91339538eeb0c62b25de4c2ea79e89e37 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Sat, 21 Mar 2020 17:16:08 +0100 Subject: synth: handle numeric_std minimum/maximum. Fix #1168 --- src/synth/netlists-disp_vhdl.adb | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'src/synth/netlists-disp_vhdl.adb') diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb index 22dc86e84..423a9ed96 100644 --- a/src/synth/netlists-disp_vhdl.adb +++ b/src/synth/netlists-disp_vhdl.adb @@ -943,6 +943,18 @@ package body Netlists.Disp_Vhdl is Disp_Template (" \o0 <= std_logic_vector (\ui0 - \ui1);" & NL, Inst); end if; + when Id_Umin => + Disp_Template (" \o0 <= \i0 when \ui0 < \ui1 else \i1;" & NL, + Inst); + when Id_Smin => + Disp_Template (" \o0 <= \i0 when \si0 < \si1 else \i1;" & NL, + Inst); + when Id_Umax => + Disp_Template (" \o0 <= \i0 when \ui0 > \ui1 else \i1;" & NL, + Inst); + when Id_Smax => + Disp_Template (" \o0 <= \i0 when \si0 > \si1 else \i1;" & NL, + Inst); when Id_Umul => Disp_Template (" \o0 <= std_logic_vector (resize (\ui0 * \ui1, \n0));" & NL, -- cgit v1.2.3