From 2a51f0c5c65d5d71c5abbd0631a0ec5660678520 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Fri, 16 Sep 2022 19:55:00 +0200 Subject: synth: preliminary work to factorize code --- src/synth/elab-vhdl_decls.adb | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) (limited to 'src/synth/elab-vhdl_decls.adb') diff --git a/src/synth/elab-vhdl_decls.adb b/src/synth/elab-vhdl_decls.adb index d7ceef8e5..5d5f38d25 100644 --- a/src/synth/elab-vhdl_decls.adb +++ b/src/synth/elab-vhdl_decls.adb @@ -295,7 +295,6 @@ package body Elab.Vhdl_Decls is Obj_Typ : Type_Acc; Base : Valtyp; Typ : Type_Acc; - Dyn : Dyn_Name; begin Mark_Expr_Pool (Marker); @@ -307,8 +306,7 @@ package body Elab.Vhdl_Decls is Obj_Typ := null; end if; - Synth_Assignment_Prefix (Syn_Inst, Get_Name (Decl), Base, Typ, Off, Dyn); - pragma Assert (Dyn = No_Dyn_Name); + Synth_Assignment_Prefix (Syn_Inst, Get_Name (Decl), Base, Typ, Off); Typ := Unshare (Typ, Instance_Pool); Res := Create_Value_Alias (Base, Off, Typ, Expr_Pool'Access); if Obj_Typ /= null then -- cgit v1.2.3