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authorTristan Gingold <tgingold@free.fr>2018-02-08 04:03:08 +0100
committerTristan Gingold <tgingold@free.fr>2018-02-08 04:03:08 +0100
commite18d42a3b9029d7210ea19b9ae343b1d0e3cde7a (patch)
tree3b240c301e9c5ec155efc2d7d08f98c85f6559ae /src/std_names.adb
parent6e2719c66ce430ed1d9ec24273a2f54035f93d87 (diff)
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std_names: add more keywords.
Diffstat (limited to 'src/std_names.adb')
-rw-r--r--src/std_names.adb8
1 files changed, 6 insertions, 2 deletions
diff --git a/src/std_names.adb b/src/std_names.adb
index f7a589210..ffee4645e 100644
--- a/src/std_names.adb
+++ b/src/std_names.adb
@@ -417,8 +417,6 @@ package body Std_Names is
Def ("vital_level1", Name_VITAL_Level1);
Def ("numeric_std", Name_Numeric_Std);
Def ("numeric_bit", Name_Numeric_Bit);
- Def ("unsigned", Name_Unsigned);
- Def ("signed", Name_Signed);
Def ("unresolved_unsigned", Name_Unresolved_Unsigned);
Def ("unresolved_signed", Name_Unresolved_Signed);
Def ("std_logic_arith", Name_Std_Logic_Arith);
@@ -500,7 +498,13 @@ package body Std_Names is
Def ("wire", Name_Wire);
Def ("wor", Name_Wor);
+ -- Verilog 2001
+ Def ("automatic", Name_Automatic);
+ Def ("endgenerate", Name_Endgenerate);
+ Def ("genvar", Name_Genvar);
Def ("localparam", Name_Localparam);
+ Def ("unsigned", Name_Unsigned);
+ Def ("signed", Name_Signed);
Def ("define", Name_Define);
Def ("endif", Name_Endif);