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| author | Tristan Gingold <tgingold@free.fr> | 2018-02-08 04:03:08 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2018-02-08 04:03:08 +0100 |
| commit | e18d42a3b9029d7210ea19b9ae343b1d0e3cde7a (patch) | |
| tree | 3b240c301e9c5ec155efc2d7d08f98c85f6559ae | |
| parent | 6e2719c66ce430ed1d9ec24273a2f54035f93d87 (diff) | |
| download | ghdl-e18d42a3b9029d7210ea19b9ae343b1d0e3cde7a.tar.gz ghdl-e18d42a3b9029d7210ea19b9ae343b1d0e3cde7a.tar.bz2 ghdl-e18d42a3b9029d7210ea19b9ae343b1d0e3cde7a.zip | |
std_names: add more keywords.
| -rw-r--r-- | src/std_names.adb | 8 | ||||
| -rw-r--r-- | src/std_names.ads | 23 |
2 files changed, 19 insertions, 12 deletions
diff --git a/src/std_names.adb b/src/std_names.adb index f7a589210..ffee4645e 100644 --- a/src/std_names.adb +++ b/src/std_names.adb @@ -417,8 +417,6 @@ package body Std_Names is Def ("vital_level1", Name_VITAL_Level1); Def ("numeric_std", Name_Numeric_Std); Def ("numeric_bit", Name_Numeric_Bit); - Def ("unsigned", Name_Unsigned); - Def ("signed", Name_Signed); Def ("unresolved_unsigned", Name_Unresolved_Unsigned); Def ("unresolved_signed", Name_Unresolved_Signed); Def ("std_logic_arith", Name_Std_Logic_Arith); @@ -500,7 +498,13 @@ package body Std_Names is Def ("wire", Name_Wire); Def ("wor", Name_Wor); + -- Verilog 2001 + Def ("automatic", Name_Automatic); + Def ("endgenerate", Name_Endgenerate); + Def ("genvar", Name_Genvar); Def ("localparam", Name_Localparam); + Def ("unsigned", Name_Unsigned); + Def ("signed", Name_Signed); Def ("define", Name_Define); Def ("endif", Name_Endif); diff --git a/src/std_names.ads b/src/std_names.ads index b078f4b72..ff273de02 100644 --- a/src/std_names.ads +++ b/src/std_names.ads @@ -492,14 +492,12 @@ package Std_Names is Name_VITAL_Level1 : constant Name_Id := Name_First_Ieee + 010; Name_Numeric_Std : constant Name_Id := Name_First_Ieee + 011; Name_Numeric_Bit : constant Name_Id := Name_First_Ieee + 012; - Name_Unsigned : constant Name_Id := Name_First_Ieee + 013; - Name_Signed : constant Name_Id := Name_First_Ieee + 014; - Name_Unresolved_Unsigned : constant Name_Id := Name_First_Ieee + 015; - Name_Unresolved_Signed : constant Name_Id := Name_First_Ieee + 016; - Name_Std_Logic_Arith : constant Name_Id := Name_First_Ieee + 017; - Name_Std_Logic_Signed : constant Name_Id := Name_First_Ieee + 018; - Name_Std_Logic_Textio : constant Name_Id := Name_First_Ieee + 019; - Name_Std_Logic_Unsigned : constant Name_Id := Name_First_Ieee + 020; + Name_Unresolved_Unsigned : constant Name_Id := Name_First_Ieee + 013; + Name_Unresolved_Signed : constant Name_Id := Name_First_Ieee + 014; + Name_Std_Logic_Arith : constant Name_Id := Name_First_Ieee + 015; + Name_Std_Logic_Signed : constant Name_Id := Name_First_Ieee + 016; + Name_Std_Logic_Textio : constant Name_Id := Name_First_Ieee + 017; + Name_Std_Logic_Unsigned : constant Name_Id := Name_First_Ieee + 018; Name_Last_Ieee : constant Name_Id := Name_Std_Logic_Unsigned; -- Verilog keywords. @@ -580,8 +578,13 @@ package Std_Names is -- Verilog 2001 Name_First_V2001 : constant Name_Id := Name_Last_Verilog + 1; - Name_Localparam : constant Name_Id := Name_First_V2001; - Name_Last_V2001 : constant Name_Id := Name_First_V2001 + 0; + Name_Automatic : constant Name_Id := Name_First_V2001 + 0; + Name_Endgenerate : constant Name_Id := Name_First_V2001 + 1; + Name_Genvar : constant Name_Id := Name_First_V2001 + 2; + Name_Localparam : constant Name_Id := Name_First_V2001 + 3; + Name_Unsigned : constant Name_Id := Name_First_V2001 + 4; + Name_Signed : constant Name_Id := Name_First_V2001 + 5; + Name_Last_V2001 : constant Name_Id := Name_First_V2001 + 5; -- Verilog Directives. Name_First_Directive : constant Name_Id := Name_Last_V2001 + 1; |