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| author | Tristan Gingold <tgingold@free.fr> | 2021-01-25 18:18:30 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2021-01-25 18:19:10 +0100 |
| commit | 6b81ec185f16791362ca770f391578c2a8b828f0 (patch) | |
| tree | 18aa0ed76886f1efc84fbb2d97358f29d4787617 /src/std_names.adb | |
| parent | ccc1c045a19345bc970a7ababb8ee0a260bd6194 (diff) | |
| download | ghdl-6b81ec185f16791362ca770f391578c2a8b828f0.tar.gz ghdl-6b81ec185f16791362ca770f391578c2a8b828f0.tar.bz2 ghdl-6b81ec185f16791362ca770f391578c2a8b828f0.zip | |
std_names: add gclk. For #1610
Regenerate python files.
Diffstat (limited to 'src/std_names.adb')
| -rw-r--r-- | src/std_names.adb | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/std_names.adb b/src/std_names.adb index 26eb53b84..4def79432 100644 --- a/src/std_names.adb +++ b/src/std_names.adb @@ -682,6 +682,7 @@ package body Std_Names is Def ("allseq", Name_Allseq); Def ("anyconst", Name_Anyconst); Def ("anyseq", Name_Anyseq); + Def ("gclk", Name_Gclk); -- Verilog directives Def ("define", Name_Define); |