From 6b81ec185f16791362ca770f391578c2a8b828f0 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Mon, 25 Jan 2021 18:18:30 +0100
Subject: std_names: add gclk.  For #1610

Regenerate python files.
---
 src/std_names.adb | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/std_names.adb')

diff --git a/src/std_names.adb b/src/std_names.adb
index 26eb53b84..4def79432 100644
--- a/src/std_names.adb
+++ b/src/std_names.adb
@@ -682,6 +682,7 @@ package body Std_Names is
       Def ("allseq",             Name_Allseq);
       Def ("anyconst",           Name_Anyconst);
       Def ("anyseq",             Name_Anyseq);
+      Def ("gclk",               Name_Gclk);
 
       --  Verilog directives
       Def ("define",          Name_Define);
-- 
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