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| author | Tristan Gingold <tgingold@free.fr> | 2023-01-18 19:15:30 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2023-01-18 19:15:30 +0100 |
| commit | d3e614c9ca81107ed059e5ed393a326265392f41 (patch) | |
| tree | 73d8cfc8154bb4a262fe2890eabe951217a32fa2 /src/simul/simul-vhdl_elab.adb | |
| parent | de7fe2bf3f78a2753809b4533fcc8575892fa000 (diff) | |
| download | ghdl-d3e614c9ca81107ed059e5ed393a326265392f41.tar.gz ghdl-d3e614c9ca81107ed059e5ed393a326265392f41.tar.bz2 ghdl-d3e614c9ca81107ed059e5ed393a326265392f41.zip | |
simul: handle PSL endpoints
Diffstat (limited to 'src/simul/simul-vhdl_elab.adb')
| -rw-r--r-- | src/simul/simul-vhdl_elab.adb | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/simul/simul-vhdl_elab.adb b/src/simul/simul-vhdl_elab.adb index 69c81be35..eb481479b 100644 --- a/src/simul/simul-vhdl_elab.adb +++ b/src/simul/simul-vhdl_elab.adb @@ -626,7 +626,8 @@ package body Simul.Vhdl_Elab is end if; when Iir_Kind_Psl_Assert_Directive | Iir_Kind_Psl_Assume_Directive - | Iir_Kind_Psl_Cover_Directive => + | Iir_Kind_Psl_Cover_Directive + | Iir_Kind_Psl_Endpoint_Declaration => List := Get_PSL_Clock_Sensitivity (Proc); Gather_Sensitivity (Inst, Proc_Idx, List); if Get_Kind (Proc) in Iir_Kinds_Psl_Property_Directive @@ -935,12 +936,12 @@ package body Simul.Vhdl_Elab is -- Do not yet compute drivers or sensitivity as it may depends -- on declarations within the process. when Iir_Kind_Psl_Default_Clock - | Iir_Kind_Psl_Declaration - | Iir_Kind_Psl_Endpoint_Declaration => + | Iir_Kind_Psl_Declaration => null; when Iir_Kind_Psl_Assert_Directive | Iir_Kind_Psl_Assume_Directive | Iir_Kind_Psl_Cover_Directive + | Iir_Kind_Psl_Endpoint_Declaration | Iir_Kind_Concurrent_Break_Statement => Processes_Table.Append ((Proc => Stmt, Inst => Inst, |