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| author | Tristan Gingold <tgingold@free.fr> | 2022-09-30 07:47:02 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-09-30 07:47:02 +0200 |
| commit | bd3f2d04cf0cb7d43bb7a823fcbdf2f5b7fdebcc (patch) | |
| tree | 0b81aa7e57efdc15be4b8e89ac094dceb350a509 /src/simul/simul-vhdl_elab.adb | |
| parent | fe092cdc810cc559ed484f480d2072c43513a04a (diff) | |
| download | ghdl-bd3f2d04cf0cb7d43bb7a823fcbdf2f5b7fdebcc.tar.gz ghdl-bd3f2d04cf0cb7d43bb7a823fcbdf2f5b7fdebcc.tar.bz2 ghdl-bd3f2d04cf0cb7d43bb7a823fcbdf2f5b7fdebcc.zip | |
simul: handle stable attribute
Diffstat (limited to 'src/simul/simul-vhdl_elab.adb')
| -rw-r--r-- | src/simul/simul-vhdl_elab.adb | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/src/simul/simul-vhdl_elab.adb b/src/simul/simul-vhdl_elab.adb index 734ff2b2e..34522853f 100644 --- a/src/simul/simul-vhdl_elab.adb +++ b/src/simul/simul-vhdl_elab.adb @@ -348,6 +348,17 @@ package body Simul.Vhdl_Elab is No_Sensitivity_Index, No_Signal_Index, T, Pfx)); end; + when Iir_Kind_Stable_Attribute => + declare + T : Std_Time; + Pfx : Sub_Signal_Type; + begin + T := Compute_Attribute_Time (Inst, Decl); + Pfx := Compute_Sub_Signal (Inst, Get_Prefix (Decl)); + Gather_Signal ((Mode_Stable, Decl, Inst, null, null, null, + No_Sensitivity_Index, No_Signal_Index, + T, Pfx)); + end; when Iir_Kind_Object_Alias_Declaration => -- In case it aliases a signal. declare |