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| author | Tristan Gingold <tgingold@free.fr> | 2023-01-14 09:42:00 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2023-01-14 09:42:00 +0100 |
| commit | 7052ac9006b145c0cd51f2bad8e088c1338f3846 (patch) | |
| tree | f64dc8ee4a4e2d308937182ca6e354156f5c211a /src/simul/simul-vhdl_elab.adb | |
| parent | 4d1eef97f13ee160e78eda631c5be1480c5f538c (diff) | |
| download | ghdl-7052ac9006b145c0cd51f2bad8e088c1338f3846.tar.gz ghdl-7052ac9006b145c0cd51f2bad8e088c1338f3846.tar.bz2 ghdl-7052ac9006b145c0cd51f2bad8e088c1338f3846.zip | |
synth: improve error propagation on slices
Diffstat (limited to 'src/simul/simul-vhdl_elab.adb')
| -rw-r--r-- | src/simul/simul-vhdl_elab.adb | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/simul/simul-vhdl_elab.adb b/src/simul/simul-vhdl_elab.adb index 0ff4d2446..69c81be35 100644 --- a/src/simul/simul-vhdl_elab.adb +++ b/src/simul/simul-vhdl_elab.adb @@ -536,7 +536,10 @@ package body Simul.Vhdl_Elab is exit when El = Null_Node; Sig := Compute_Sub_Signal (Inst, El); - Add_Process_Driver (Proc_Idx, Sig, El); + if Sig.Base /= No_Signal_Index then + -- Only if no error. + Add_Process_Driver (Proc_Idx, Sig, El); + end if; Next (It); end loop; |