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| author | Tristan Gingold <gingold@adacore.com> | 2015-12-16 09:38:00 +0100 |
|---|---|---|
| committer | Tristan Gingold <gingold@adacore.com> | 2015-12-18 17:16:27 +0100 |
| commit | e8a965f0f42749f7fbcaaee966e24a55fb45d886 (patch) | |
| tree | 448d507f7074f78e80dd4afe5b983609a08396ca /src/grt/grt-vpi.adb | |
| parent | 4680da5edb910910c4a31438798bff0bc6e51380 (diff) | |
| download | ghdl-e8a965f0f42749f7fbcaaee966e24a55fb45d886.tar.gz ghdl-e8a965f0f42749f7fbcaaee966e24a55fb45d886.tar.bz2 ghdl-e8a965f0f42749f7fbcaaee966e24a55fb45d886.zip | |
Pass signal values to interfaces. 'sigptr' optimization.
Improve simulation speed by about 20%.
Diffstat (limited to 'src/grt/grt-vpi.adb')
| -rw-r--r-- | src/grt/grt-vpi.adb | 5 |
1 files changed, 2 insertions, 3 deletions
diff --git a/src/grt/grt-vpi.adb b/src/grt/grt-vpi.adb index eedb8460c..136010a77 100644 --- a/src/grt/grt-vpi.adb +++ b/src/grt/grt-vpi.adb @@ -478,12 +478,12 @@ package body Grt.Vpi is | Vcd_Bool | Vcd_Bitvector => for J in 0 .. Len - 1 loop - ii_vpi_get_value_bin_str_B1 (Info.Sigs (J).Value.B1); + ii_vpi_get_value_bin_str_B1 (Info.Sigs (J).Value_Ptr.B1); end loop; when Vcd_Stdlogic | Vcd_Stdlogic_Vector => for J in 0 .. Len - 1 loop - ii_vpi_get_value_bin_str_E8 (Info.Sigs (J).Value.E8); + ii_vpi_get_value_bin_str_E8 (Info.Sigs (J).Value_Ptr.E8); end loop; end case; when Vcd_Driving => @@ -571,7 +571,6 @@ package body Grt.Vpi is -- Alter the simulation value of an object. -- see IEEE 1364-2001, chapter 27.14, page 675 -- FIXME - type Std_Ulogic_Array is array (Ghdl_Index_Type range <>) of Std_Ulogic; procedure Ii_Vpi_Put_Value (Info : Verilog_Wire_Info; |