From e8a965f0f42749f7fbcaaee966e24a55fb45d886 Mon Sep 17 00:00:00 2001 From: Tristan Gingold Date: Wed, 16 Dec 2015 09:38:00 +0100 Subject: Pass signal values to interfaces. 'sigptr' optimization. Improve simulation speed by about 20%. --- src/grt/grt-vpi.adb | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) (limited to 'src/grt/grt-vpi.adb') diff --git a/src/grt/grt-vpi.adb b/src/grt/grt-vpi.adb index eedb8460c..136010a77 100644 --- a/src/grt/grt-vpi.adb +++ b/src/grt/grt-vpi.adb @@ -478,12 +478,12 @@ package body Grt.Vpi is | Vcd_Bool | Vcd_Bitvector => for J in 0 .. Len - 1 loop - ii_vpi_get_value_bin_str_B1 (Info.Sigs (J).Value.B1); + ii_vpi_get_value_bin_str_B1 (Info.Sigs (J).Value_Ptr.B1); end loop; when Vcd_Stdlogic | Vcd_Stdlogic_Vector => for J in 0 .. Len - 1 loop - ii_vpi_get_value_bin_str_E8 (Info.Sigs (J).Value.E8); + ii_vpi_get_value_bin_str_E8 (Info.Sigs (J).Value_Ptr.E8); end loop; end case; when Vcd_Driving => @@ -571,7 +571,6 @@ package body Grt.Vpi is -- Alter the simulation value of an object. -- see IEEE 1364-2001, chapter 27.14, page 675 -- FIXME - type Std_Ulogic_Array is array (Ghdl_Index_Type range <>) of Std_Ulogic; procedure Ii_Vpi_Put_Value (Info : Verilog_Wire_Info; -- cgit v1.2.3