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authorTristan Gingold <tgingold@free.fr>2016-07-02 21:06:01 +0200
committerTristan Gingold <tgingold@free.fr>2016-07-03 16:34:21 +0200
commit3f72c841aba4555ba511c303074ffb2896e9551e (patch)
tree5707fd45ec626a6bce117ebcd19d966e70f1a845 /src/grt/grt-vcd.ads
parent33ea6a40fa3987eb13ae719c4b229b5df7732e2f (diff)
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grt-vcd: rename vcd_var_kind to vcd_var_type.
Diffstat (limited to 'src/grt/grt-vcd.ads')
-rw-r--r--src/grt/grt-vcd.ads8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/grt/grt-vcd.ads b/src/grt/grt-vcd.ads
index c2755d253..566901dfc 100644
--- a/src/grt/grt-vcd.ads
+++ b/src/grt/grt-vcd.ads
@@ -39,7 +39,7 @@ package Grt.Vcd is
Vcd_Close : Vcd_Close_Acc;
-- VCD type of an object
- type Vcd_Var_Kind is
+ type Vcd_Var_Type is
(
-- Incompatible vcd type
Vcd_Bad,
@@ -63,19 +63,19 @@ package Grt.Vcd is
Vcd_Bitvector, Vcd_Stdlogic_Vector
);
- subtype Vcd_Var_Vectors is Vcd_Var_Kind
+ subtype Vcd_Var_Vectors is Vcd_Var_Type
range Vcd_Bitvector .. Vcd_Stdlogic_Vector;
-- Which value to be displayed: effective or driving (for out signals).
type Vcd_Value_Kind is (Vcd_Effective, Vcd_Driving);
- type Verilog_Wire_Info (Kind : Vcd_Var_Kind := Vcd_Bad) is record
+ type Verilog_Wire_Info (Vtype : Vcd_Var_Type := Vcd_Bad) is record
Val : Vcd_Value_Kind;
-- Access to an array of signals.
Sigs : Grt.Signals.Signal_Arr_Ptr;
- case Kind is
+ case Vtype is
when Vcd_Var_Vectors =>
-- Vector bounds.
Irange : Ghdl_Range_Ptr;