grt-vcd: rename vcd_var_kind to vcd_var_type.

4 files changed, 32 insertions, 37 deletions

diff --git a/src/grt/grt-fst.adb b/src/grt/grt-fst.adb
index 506d01cfa..98403b69e 100644
--- a/src/grt/grt-fst.adb
+++ b/src/grt/grt-fst.adb
@@ -123,7 +123,7 @@ package body Grt.Fst is
    is
       Len : Ghdl_Index_Type;
    begin
-      if Left.Kind /= Right.Kind
+      if Left.Vtype /= Right.Vtype
         or else Left.Val /= Right.Val
       then
          return False;
@@ -150,7 +150,7 @@ package body Grt.Fst is
       Res : Ghdl_Index_Type;
       Iaddr : Integer_Address;
    begin
-      Res := Vcd_Var_Kind'Pos (El.Kind) * 2 + Vcd_Value_Kind'Pos (El.Val);
+      Res := Vcd_Var_Type'Pos (El.Vtype) * 2 + Vcd_Value_Kind'Pos (El.Val);
       Res := Res + Len * 29;
       for I in 1 .. Len loop
          Iaddr := To_Integer (El.Sigs (I - 1).all'Address);
@@ -213,7 +213,7 @@ package body Grt.Fst is
    begin
       Get_Verilog_Wire (Sig, Vcd_El);
 
-      case Vcd_El.Kind is
+      case Vcd_El.Vtype is
          when Vcd_Bad =>
             --  Not handled.
             return;
@@ -336,7 +336,7 @@ package body Grt.Fst is
       --  Extract name (avoid truncation, append verilog range for arrays).
       Vhpi_Get_Str (VhpiNameP, Sig, Name, Name_Len);
       if Name_Len >= Name'Length
-        or else Vcd_El.Kind in Vcd_Var_Vectors
+        or else Vcd_El.Vtype in Vcd_Var_Vectors
       then
          declare
             Name2 : String (1 .. Name_Len + 3 + 2 * 11 + 1);
@@ -540,18 +540,13 @@ package body Grt.Fst is
       type Map_Type is array (Ghdl_E8 range 0 .. 8) of Character;
       From_Std : constant Map_Type := "UX01ZWLH-";
       V : Fst_Sig_Info renames Fst_Table.Table (I);
-      Len : Ghdl_Index_Type;
+      Len : constant Ghdl_Index_Type := Get_Wire_Length (V.Wire);
       Hand : constant fstHandle := V.Hand;
       Sig : constant Signal_Arr_Ptr := V.Wire.Sigs;
    begin
-      if V.Wire.Kind not in Vcd_Var_Vectors then
-         Len := 1;
-      else
-         Len := V.Wire.Irange.I32.Len;
-      end if;
       case V.Wire.Val is
          when Vcd_Effective =>
-            case V.Wire.Kind is
+            case V.Wire.Vtype is
                when Vcd_Bit
                  | Vcd_Bool
                  | Vcd_Bitvector =>
@@ -583,7 +578,7 @@ package body Grt.Fst is
                   null;
             end case;
          when Vcd_Driving =>
-            case V.Wire.Kind is
+            case V.Wire.Vtype is
                when Vcd_Bit
                  | Vcd_Bool
                  | Vcd_Bitvector =>
diff --git a/src/grt/grt-vcd.adb b/src/grt/grt-vcd.adb
index 4a9153643..d7b223a16 100644
--- a/src/grt/grt-vcd.adb
+++ b/src/grt/grt-vcd.adb
@@ -244,7 +244,7 @@ package body Grt.Vcd is
       null;
    end Avhpi_Error;
 
-   function Rti_To_Vcd_Kind (Rti : Ghdl_Rti_Access) return Vcd_Var_Kind is
+   function Rti_To_Vcd_Kind (Rti : Ghdl_Rti_Access) return Vcd_Var_Type is
    begin
       case Rti.Kind is
          when Ghdl_Rtik_Subtype_Scalar =>
@@ -274,7 +274,7 @@ package body Grt.Vcd is
    end Rti_To_Vcd_Kind;
 
    function Rti_To_Vcd_Kind (Rti : Ghdl_Rtin_Type_Array_Acc)
-                            return Vcd_Var_Kind
+                            return Vcd_Var_Type
    is
       It : Ghdl_Rti_Access;
    begin
@@ -313,7 +313,7 @@ package body Grt.Vcd is
       Error : AvhpiErrorT;
       Sig_Addr : Address;
 
-      Kind : Vcd_Var_Kind;
+      Kind : Vcd_Var_Type;
       Sigs : Grt.Signals.Signal_Arr_Ptr;
       Irange : Ghdl_Range_Ptr;
       Val : Vcd_Value_Kind;
@@ -365,7 +365,7 @@ package body Grt.Vcd is
 
       --  Do not allow null-array.
       if Irange /= null and then Irange.I32.Len = 0 then
-         Info := (Kind => Vcd_Bad, Val => Vcd_Effective, Sigs => null);
+         Info := (Vtype => Vcd_Bad, Val => Vcd_Effective, Sigs => null);
          return;
       end if;
 
@@ -410,7 +410,7 @@ package body Grt.Vcd is
    function Get_Wire_Length (Info : Verilog_Wire_Info)
                             return Ghdl_Index_Type is
    begin
-      if Info.Kind in Vcd_Var_Vectors then
+      if Info.Vtype in Vcd_Var_Vectors then
          return Info.Irange.I32.Len;
       else
          return 1;
@@ -424,8 +424,8 @@ package body Grt.Vcd is
    begin
       Get_Verilog_Wire (Sig, Vcd_El);
 
-      if Vcd_El.Kind = Vcd_Bad
-        or else Vcd_El.Kind = Vcd_Enum8
+      if Vcd_El.Vtype = Vcd_Bad
+        or else Vcd_El.Vtype = Vcd_Enum8
       then
          Vcd_Put ("$comment ");
          Vcd_Put_Name (Sig);
@@ -440,7 +440,7 @@ package body Grt.Vcd is
 
          Vcd_Table.Table (N) := Vcd_El;
          Vcd_Put ("$var ");
-         case Vcd_El.Kind is
+         case Vcd_El.Vtype is
             when Vcd_Integer32 =>
                Vcd_Put ("integer 32");
             when Vcd_Float64 =>
@@ -461,7 +461,7 @@ package body Grt.Vcd is
          Vcd_Put_Idcode (N);
          Vcd_Putc (' ');
          Vcd_Put_Name (Sig);
-         if Vcd_El.Kind in Vcd_Var_Vectors then
+         if Vcd_El.Vtype in Vcd_Var_Vectors then
             Vcd_Putc ('[');
             Vcd_Put_I32 (Vcd_El.Irange.I32.Left);
             Vcd_Putc (':');
@@ -687,7 +687,7 @@ package body Grt.Vcd is
    begin
       case V.Val is
          when Vcd_Effective =>
-            case V.Kind is
+            case V.Vtype is
                when Vcd_Bit
                  | Vcd_Bool =>
                   Vcd_Put_Bit (V.Sigs (0).Value_Ptr.B1);
@@ -718,7 +718,7 @@ package body Grt.Vcd is
                   null;
             end case;
          when Vcd_Driving =>
-            case V.Kind is
+            case V.Vtype is
                when Vcd_Bit
                  | Vcd_Bool =>
                   Vcd_Put_Bit (V.Sigs (0).Driving_Value.B1);
@@ -760,7 +760,7 @@ package body Grt.Vcd is
    begin
       case Info.Val is
          when Vcd_Effective =>
-            case Info.Kind is
+            case Info.Vtype is
                when Vcd_Bit
                  | Vcd_Bool
                  | Vcd_Enum8
@@ -778,7 +778,7 @@ package body Grt.Vcd is
                   null;
             end case;
          when Vcd_Driving =>
-            case Info.Kind is
+            case Info.Vtype is
                when Vcd_Bit
                  | Vcd_Bool
                  | Vcd_Enum8
@@ -803,7 +803,7 @@ package body Grt.Vcd is
    is
       Len : constant Ghdl_Index_Type := Get_Wire_Length (Info);
    begin
-      case Info.Kind is
+      case Info.Vtype is
          when Vcd_Bit
            | Vcd_Bool
            | Vcd_Enum8
diff --git a/src/grt/grt-vcd.ads b/src/grt/grt-vcd.ads
index c2755d253..566901dfc 100644
--- a/src/grt/grt-vcd.ads
+++ b/src/grt/grt-vcd.ads
@@ -39,7 +39,7 @@ package Grt.Vcd is
    Vcd_Close : Vcd_Close_Acc;
 
    --  VCD type of an object
-   type Vcd_Var_Kind is
+   type Vcd_Var_Type is
      (
       --  Incompatible vcd type
       Vcd_Bad,
@@ -63,19 +63,19 @@ package Grt.Vcd is
       Vcd_Bitvector, Vcd_Stdlogic_Vector
      );
 
-   subtype Vcd_Var_Vectors is Vcd_Var_Kind
+   subtype Vcd_Var_Vectors is Vcd_Var_Type
      range Vcd_Bitvector .. Vcd_Stdlogic_Vector;
 
    --  Which value to be displayed: effective or driving (for out signals).
    type Vcd_Value_Kind is (Vcd_Effective, Vcd_Driving);
 
-   type Verilog_Wire_Info (Kind : Vcd_Var_Kind := Vcd_Bad) is record
+   type Verilog_Wire_Info (Vtype : Vcd_Var_Type := Vcd_Bad) is record
       Val : Vcd_Value_Kind;
 
       --  Access to an array of signals.
       Sigs : Grt.Signals.Signal_Arr_Ptr;
 
-      case Kind is
+      case Vtype is
          when Vcd_Var_Vectors =>
             --  Vector bounds.
             Irange : Ghdl_Range_Ptr;
diff --git a/src/grt/grt-vpi.adb b/src/grt/grt-vpi.adb
index e3567c268..d4a2d2d97 100644
--- a/src/grt/grt-vpi.adb
+++ b/src/grt/grt-vpi.adb
@@ -418,7 +418,7 @@ package body Grt.Vpi is
       Info : Verilog_Wire_Info;
    begin
       Get_Verilog_Wire (Ref.Ref, Info);
-      if Info.Kind /= Vcd_Bad then
+      if Info.Vtype /= Vcd_Bad then
          return Natural (Get_Wire_Length (Info));
       else
          return 0;
@@ -430,7 +430,7 @@ package body Grt.Vpi is
       Info : Verilog_Wire_Info;
    begin
       Get_Verilog_Wire (Ref.Ref, Info);
-      case Info.Kind is
+      case Info.Vtype is
          when Vcd_Bool
            | Vcd_Integer32
            | Vcd_Float64
@@ -763,7 +763,7 @@ package body Grt.Vpi is
 
       --  Get verilog compat info.
       Get_Verilog_Wire (Obj, Info);
-      if Info.Kind = Vcd_Bad then
+      if Info.Vtype = Vcd_Bad then
          return null;
       end if;
 
@@ -773,7 +773,7 @@ package body Grt.Vpi is
 
       case Info.Val is
          when Vcd_Effective =>
-            case Info.Kind is
+            case Info.Vtype is
                when Vcd_Bad
                  | Vcd_Enum8
                  | Vcd_Integer32
@@ -794,7 +794,7 @@ package body Grt.Vpi is
                   end loop;
             end case;
          when Vcd_Driving =>
-            case Info.Kind is
+            case Info.Vtype is
                when Vcd_Bad
                  | Vcd_Enum8
                  | Vcd_Integer32
@@ -895,7 +895,7 @@ package body Grt.Vpi is
    procedure Ii_Vpi_Put_Value (Info : Verilog_Wire_Info;
                                Vec : Std_Ulogic_Array) is
    begin
-      case Info.Kind is
+      case Info.Vtype is
          when Vcd_Bad =>
             return;
          when Vcd_Bit
@@ -1038,7 +1038,7 @@ package body Grt.Vpi is
       -- ii_vpi_get_value function.
       --  Get verilog compat info.
       Get_Verilog_Wire (aObj.Ref, Info);
-      if Info.Kind = Vcd_Bad then
+      if Info.Vtype = Vcd_Bad then
          return null;
       end if;