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| author | Tristan Gingold <tgingold@free.fr> | 2021-04-28 21:23:59 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2021-04-28 21:39:06 +0200 |
| commit | 9fb3ee1a53f26909a14090a7f7fc70bf149a670e (patch) | |
| tree | 2b3bffdf14426aaf9357cadb1b10f79bab5d937c /src/ghdldrv | |
| parent | 199dd673c7c68c40f0ab672869a8b8b04c349860 (diff) | |
| download | ghdl-9fb3ee1a53f26909a14090a7f7fc70bf149a670e.tar.gz ghdl-9fb3ee1a53f26909a14090a7f7fc70bf149a670e.tar.bz2 ghdl-9fb3ee1a53f26909a14090a7f7fc70bf149a670e.zip | |
ghdlsynth: never display a foreign module as pure vhdl
(do not try to display the original entity when this is none)
Diffstat (limited to 'src/ghdldrv')
| -rw-r--r-- | src/ghdldrv/ghdlsynth.adb | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/src/ghdldrv/ghdlsynth.adb b/src/ghdldrv/ghdlsynth.adb index 890be63ec..5d76355aa 100644 --- a/src/ghdldrv/ghdlsynth.adb +++ b/src/ghdldrv/ghdlsynth.adb @@ -439,8 +439,13 @@ package body Ghdlsynth is when Format_Dot => Netlists.Disp_Dot.Disp_Dot_Top_Module (Res); when Format_Vhdl => - Ent := Vhdl.Utils.Get_Entity_From_Configuration (Config); - Synth.Disp_Vhdl.Disp_Vhdl_Wrapper (Ent, Res, Inst); + if Get_Kind (Config) = Iir_Kind_Foreign_Module then + -- Not a VHDL design. + Netlists.Disp_Vhdl.Disp_Vhdl (Res); + else + Ent := Vhdl.Utils.Get_Entity_From_Configuration (Config); + Synth.Disp_Vhdl.Disp_Vhdl_Wrapper (Ent, Res, Inst); + end if; when Format_Raw_Vhdl => Netlists.Disp_Vhdl.Disp_Vhdl (Res); when Format_Verilog => |