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| author | Tristan Gingold <tgingold@free.fr> | 2022-06-14 05:51:55 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-06-14 05:51:55 +0200 |
| commit | 02901338441cc151c746fe7f181d27194bea6fd0 (patch) | |
| tree | febcd034a90dfac4794af018383be6036d2cb1a7 /src/ghdldrv | |
| parent | 1a789146110f65b78df8595fb28d62cf79ab0b1b (diff) | |
| download | ghdl-02901338441cc151c746fe7f181d27194bea6fd0.tar.gz ghdl-02901338441cc151c746fe7f181d27194bea6fd0.tar.bz2 ghdl-02901338441cc151c746fe7f181d27194bea6fd0.zip | |
src/synth: add netlists.rename to rename identifiers. Fix #2054
Diffstat (limited to 'src/ghdldrv')
| -rw-r--r-- | src/ghdldrv/ghdlsynth.adb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/ghdldrv/ghdlsynth.adb b/src/ghdldrv/ghdlsynth.adb index 264960ffc..8ee8e02d8 100644 --- a/src/ghdldrv/ghdlsynth.adb +++ b/src/ghdldrv/ghdlsynth.adb @@ -44,6 +44,7 @@ with Netlists.Disp_Verilog; with Netlists.Disp_Dot; with Netlists.Errors; with Netlists.Inference; +with Netlists.Rename; with Elab.Vhdl_Context; use Elab.Vhdl_Context; with Elab.Vhdl_Insts; @@ -452,6 +453,7 @@ package body Ghdlsynth is when Format_Raw_Vhdl => Netlists.Disp_Vhdl.Disp_Vhdl (Res); when Format_Verilog => + Netlists.Rename.Rename_Module (Res, Language_Verilog); Netlists.Disp_Verilog.Disp_Verilog (Res); end case; end Disp_Design; |