diff options
| -rw-r--r-- | src/ghdldrv/ghdlsynth.adb | 2 | ||||
| -rw-r--r-- | src/synth/netlists-rename.adb | 109 | ||||
| -rw-r--r-- | src/synth/netlists-rename.ads | 21 | ||||
| -rw-r--r-- | src/synth/netlists.adb | 2 |
4 files changed, 132 insertions, 2 deletions
diff --git a/src/ghdldrv/ghdlsynth.adb b/src/ghdldrv/ghdlsynth.adb index 264960ffc..8ee8e02d8 100644 --- a/src/ghdldrv/ghdlsynth.adb +++ b/src/ghdldrv/ghdlsynth.adb @@ -44,6 +44,7 @@ with Netlists.Disp_Verilog; with Netlists.Disp_Dot; with Netlists.Errors; with Netlists.Inference; +with Netlists.Rename; with Elab.Vhdl_Context; use Elab.Vhdl_Context; with Elab.Vhdl_Insts; @@ -452,6 +453,7 @@ package body Ghdlsynth is when Format_Raw_Vhdl => Netlists.Disp_Vhdl.Disp_Vhdl (Res); when Format_Verilog => + Netlists.Rename.Rename_Module (Res, Language_Verilog); Netlists.Disp_Verilog.Disp_Verilog (Res); end case; end Disp_Design; diff --git a/src/synth/netlists-rename.adb b/src/synth/netlists-rename.adb new file mode 100644 index 000000000..afa0e4c83 --- /dev/null +++ b/src/synth/netlists-rename.adb @@ -0,0 +1,109 @@ +-- Renaming to avoid use of keywords. +-- Copyright (C) 2022 Tristan Gingold +-- +-- This file is part of GHDL. +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see <gnu.org/licenses>. + +with Name_Table; +with Std_Names; + +package body Netlists.Rename is + function Rename_Sname (Name : Sname; Lang : Language_Type) return Sname + is + use Name_Table; + use Std_Names; + Id : Name_Id; + Res : String (1 .. 12); + Len : Positive; + begin + if Get_Sname_Kind (Name) /= Sname_User then + return Name; + end if; + if Get_Sname_Prefix (Name) /= No_Sname then + return Name; + end if; + + Id := Get_Sname_Suffix (Name); + + pragma Assert (Lang = Language_Verilog); + + case Id is + when Name_First_Verilog .. Name_Last_V2001 => + null; + when Name_Xnor + | Name_Nor + | Name_Nand + | Name_Xor + | Name_Or + | Name_And + | Name_Begin + | Name_Case + | Name_Else + | Name_End + | Name_For + | Name_Function + | Name_If + | Name_Inout + | Name_Not + | Name_While + | Name_Wait => + null; + when others => + -- Not a keyword + return Name; + end case; + + Len := Get_Name_Length (Id); + Res (2 .. Len + 1) := Image (Id); + Res (1) := '\'; + Res (Len + 2) := ' '; + Id := Get_Identifier (Res (1 .. Len + 2)); + return New_Sname_User (Id, No_Sname); + end Rename_Sname; + + procedure Rename_User_Module (M : Module; Lang : Language_Type) + is + Port : Port_Desc; + begin + -- Rename inputs and outputs. + for I in 1 .. Get_Nbr_Inputs (M) loop + Port := Get_Input_Desc (M, I - 1); + Port.Name := Rename_Sname (Port.Name, Lang); + Set_Input_Desc (M, I - 1, Port); + end loop; + for I in 1 .. Get_Nbr_Outputs (M) loop + Port := Get_Output_Desc (M, I - 1); + Port.Name := Rename_Sname (Port.Name, Lang); + Set_Output_Desc (M, I - 1, Port); + end loop; + + -- rename instances ? + -- rename module name ? + -- rename parameters ? + end Rename_User_Module; + + procedure Rename_Module (M : Module; Lang : Language_Type) + is + Sm : Module; + begin + Sm := Get_First_Sub_Module (M); + while Sm /= No_Module loop + if Get_Id (Sm) >= Id_User_None then + Rename_User_Module (Sm, Lang); + end if; + Sm := Get_Next_Sub_Module (Sm); + end loop; + end Rename_Module; +end Netlists.Rename; diff --git a/src/synth/netlists-rename.ads b/src/synth/netlists-rename.ads new file mode 100644 index 000000000..45e5008b5 --- /dev/null +++ b/src/synth/netlists-rename.ads @@ -0,0 +1,21 @@ +-- Renaming to avoid use of keywords. +-- Copyright (C) 2022 Tristan Gingold +-- +-- This file is part of GHDL. +-- +-- This program is free software: you can redistribute it and/or modify +-- it under the terms of the GNU General Public License as published by +-- the Free Software Foundation, either version 2 of the License, or +-- (at your option) any later version. +-- +-- This program is distributed in the hope that it will be useful, +-- but WITHOUT ANY WARRANTY; without even the implied warranty of +-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +-- GNU General Public License for more details. +-- +-- You should have received a copy of the GNU General Public License +-- along with this program. If not, see <gnu.org/licenses>. + +package Netlists.Rename is + procedure Rename_Module (M : Module; Lang : Language_Type); +end Netlists.Rename; diff --git a/src/synth/netlists.adb b/src/synth/netlists.adb index 5ea2b9b90..f872606e2 100644 --- a/src/synth/netlists.adb +++ b/src/synth/netlists.adb @@ -878,7 +878,6 @@ package body Netlists is pragma Assert (I < Get_Nbr_Inputs (M)); Idx : constant Port_Desc_Idx := F + Port_Desc_Idx (I); begin - pragma Assert (Get_Port_Desc (Idx).Name = No_Sname); Set_Port_Desc (Idx, Desc); end Set_Input_Desc; @@ -888,7 +887,6 @@ package body Netlists is pragma Assert (O < Get_Nbr_Outputs (M)); Idx : constant Port_Desc_Idx := F + Port_Desc_Idx (O); begin - pragma Assert (Get_Port_Desc (Idx).Name = No_Sname); Set_Port_Desc (Idx, Desc); end Set_Output_Desc; |