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| author | Patrick Lehmann <Patrick.Lehmann@plc2.de> | 2021-08-06 20:11:33 +0200 |
|---|---|---|
| committer | umarcor <unai.martinezcorral@ehu.eus> | 2021-08-23 16:35:34 +0200 |
| commit | c80c2e02dda356e3eb00ae6a097ff62c0f08fc79 (patch) | |
| tree | a12e825b61b62e64ef0f3f40d5619636858fda20 /pyGHDL/dom | |
| parent | 407f07a7b3100020bb9f5dbe5863c0b8b45cdd9d (diff) | |
| download | ghdl-c80c2e02dda356e3eb00ae6a097ff62c0f08fc79.tar.gz ghdl-c80c2e02dda356e3eb00ae6a097ff62c0f08fc79.tar.bz2 ghdl-c80c2e02dda356e3eb00ae6a097ff62c0f08fc79.zip | |
Renamed to ConcurrentSimpleSignalAssignment.
Diffstat (limited to 'pyGHDL/dom')
| -rw-r--r-- | pyGHDL/dom/Concurrent.py | 2 | ||||
| -rw-r--r-- | pyGHDL/dom/_Translate.py | 4 |
2 files changed, 3 insertions, 3 deletions
diff --git a/pyGHDL/dom/Concurrent.py b/pyGHDL/dom/Concurrent.py index f57f4fa49..ab30f9176 100644 --- a/pyGHDL/dom/Concurrent.py +++ b/pyGHDL/dom/Concurrent.py @@ -44,7 +44,7 @@ from pyVHDLModel.SyntaxModel import ( IfGenerateStatement as VHDLModel_IfGenerateStatement, CaseGenerateStatement as VHDLModel_CaseGenerateStatement, ForGenerateStatement as VHDLModel_ForGenerateStatement, - ConcurrentSignalAssignment as VHDLModel_ConcurrentSignalAssignment, + ConcurrentSimpleSignalAssignment as VHDLModel_ConcurrentSimpleSignalAssignment, Name, ConcurrentStatement, SequentialStatement, diff --git a/pyGHDL/dom/_Translate.py b/pyGHDL/dom/_Translate.py index 32e2c45f7..b53b7976e 100644 --- a/pyGHDL/dom/_Translate.py +++ b/pyGHDL/dom/_Translate.py @@ -147,7 +147,7 @@ from pyGHDL.dom.Concurrent import ( IfGenerateStatement, ForGenerateStatement, CaseGenerateStatement, - ConcurrentSignalAssignment, + ConcurrentSimpleSignalAssignment, ) from pyGHDL.dom.Subprogram import Function, Procedure from pyGHDL.dom.Misc import Alias @@ -801,7 +801,7 @@ def GetStatementsFromChainedNodes( yield ProcessStatement.parse(statement, label, False) elif kind == nodes.Iir_Kind.Concurrent_Simple_Signal_Assignment: - yield ConcurrentSignalAssignment.parse(statement, label) + yield ConcurrentSimpleSignalAssignment.parse(statement, label) elif kind == nodes.Iir_Kind.Concurrent_Conditional_Signal_Assignment: print( "[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: '{label}') at line {line}".format( |