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| author | Patrick Lehmann <Patrick.Lehmann@plc2.de> | 2021-08-02 11:52:48 +0200 |
|---|---|---|
| committer | umarcor <unai.martinezcorral@ehu.eus> | 2021-08-23 16:35:34 +0200 |
| commit | 407f07a7b3100020bb9f5dbe5863c0b8b45cdd9d (patch) | |
| tree | 27d4f3ce85e3afcdc3afaca4b4cacb7340f8aa35 /pyGHDL/dom | |
| parent | 2a571db9fecf39cc593b0a5666a540ef5cdc39fc (diff) | |
| download | ghdl-407f07a7b3100020bb9f5dbe5863c0b8b45cdd9d.tar.gz ghdl-407f07a7b3100020bb9f5dbe5863c0b8b45cdd9d.tar.bz2 ghdl-407f07a7b3100020bb9f5dbe5863c0b8b45cdd9d.zip | |
Added handling of simple concurrent statements.
Diffstat (limited to 'pyGHDL/dom')
| -rw-r--r-- | pyGHDL/dom/Concurrent.py | 38 | ||||
| -rw-r--r-- | pyGHDL/dom/_Translate.py | 7 |
2 files changed, 37 insertions, 8 deletions
diff --git a/pyGHDL/dom/Concurrent.py b/pyGHDL/dom/Concurrent.py index 6b07ff3ae..f57f4fa49 100644 --- a/pyGHDL/dom/Concurrent.py +++ b/pyGHDL/dom/Concurrent.py @@ -44,6 +44,7 @@ from pyVHDLModel.SyntaxModel import ( IfGenerateStatement as VHDLModel_IfGenerateStatement, CaseGenerateStatement as VHDLModel_CaseGenerateStatement, ForGenerateStatement as VHDLModel_ForGenerateStatement, + ConcurrentSignalAssignment as VHDLModel_ConcurrentSignalAssignment, Name, ConcurrentStatement, SequentialStatement, @@ -255,9 +256,9 @@ class IfGenerateStatement(VHDLModel_IfGenerateStatement, DOMMixin): print(generateNode, GetIirKindOfNode(generateNode)) ifBranch = IfGenerateBranch.parse(generateNode) -# Python 3.8 syntax -# elseClause = generateNode -# while (elseClause := nodes.Get_Generate_Else_Clause(elseClause)) != nodes.Null_Iir: + # Python 3.8 syntax + # elseClause = generateNode + # while (elseClause := nodes.Get_Generate_Else_Clause(elseClause)) != nodes.Null_Iir: elseClause = nodes.Get_Generate_Else_Clause(generateNode) while elseClause != nodes.Null_Iir: print(elseClause, GetIirKindOfNode(elseClause)) @@ -295,3 +296,34 @@ class ForGenerateStatement(VHDLModel_ForGenerateStatement, DOMMixin): # TODO: get concurrent statements return cls(generateNode, label) + + +@export +class ConcurrentSimpleSignalAssignment( + VHDLModel_ConcurrentSimpleSignalAssignment, DOMMixin +): + def __init__( + self, + assignmentNode: Iir, + target: Name, + expression: Expression, + label: str = None, + ): + super().__init__(target, expression, label) + DOMMixin.__init__(self, assignmentNode) + + @classmethod + def parse( + cls, assignmentNode: Iir, label: str + ) -> "ConcurrentSimpleSignalAssignment": + from pyGHDL.dom._Translate import GetNameFromNode + + target = nodes.Get_Target(assignmentNode) + targetName = GetNameFromNode(target) + + waveform = nodes.Get_Waveform_Chain(assignmentNode) + + # TODO: translate waveforms to series of "expressions". + expression = None + + return cls(assignmentNode, targetName, expression, label) diff --git a/pyGHDL/dom/_Translate.py b/pyGHDL/dom/_Translate.py index 44915c026..32e2c45f7 100644 --- a/pyGHDL/dom/_Translate.py +++ b/pyGHDL/dom/_Translate.py @@ -147,6 +147,7 @@ from pyGHDL.dom.Concurrent import ( IfGenerateStatement, ForGenerateStatement, CaseGenerateStatement, + ConcurrentSignalAssignment, ) from pyGHDL.dom.Subprogram import Function, Procedure from pyGHDL.dom.Misc import Alias @@ -800,11 +801,7 @@ def GetStatementsFromChainedNodes( yield ProcessStatement.parse(statement, label, False) elif kind == nodes.Iir_Kind.Concurrent_Simple_Signal_Assignment: - print( - "[NOT IMPLEMENTED] Concurrent (simple) signal assignment (label: '{label}') at line {line}".format( - label=label, line=pos.Line - ) - ) + yield ConcurrentSignalAssignment.parse(statement, label) elif kind == nodes.Iir_Kind.Concurrent_Conditional_Signal_Assignment: print( "[NOT IMPLEMENTED] Concurrent (conditional) signal assignment (label: '{label}') at line {line}".format( |