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authorPatrick Lehmann <Patrick.Lehmann@plc2.de>2021-08-23 09:02:47 +0200
committerumarcor <unai.martinezcorral@ehu.eus>2021-08-23 16:35:37 +0200
commit8b98e2883b40b00922c9944c2470211ee055a9a5 (patch)
tree05a31686d247ef71cb512ac79643f3a309e72eeb /pyGHDL/dom/Sequential.py
parent8fb4da723067b2ff99050f9ef9fc0bbd3c835ef4 (diff)
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Fixes due to a bug in pyVHDLModel. Name Context was used twice.
Diffstat (limited to 'pyGHDL/dom/Sequential.py')
-rw-r--r--pyGHDL/dom/Sequential.py24
1 files changed, 12 insertions, 12 deletions
diff --git a/pyGHDL/dom/Sequential.py b/pyGHDL/dom/Sequential.py
index 4f511c16f..be4793b2a 100644
--- a/pyGHDL/dom/Sequential.py
+++ b/pyGHDL/dom/Sequential.py
@@ -57,7 +57,7 @@ from pyVHDLModel.SyntaxModel import (
WaitStatement as VHDLModel_WaitStatement,
Name,
SequentialStatement,
- Expression,
+ ExpressionUnion,
SequentialChoice,
SequentialCase,
)
@@ -74,7 +74,7 @@ class IfBranch(VHDLModel_IfBranch):
def __init__(
self,
branchNode: Iir,
- condition: Expression,
+ condition: ExpressionUnion,
statements: Iterable[SequentialStatement] = None,
):
super().__init__(condition, statements)
@@ -101,7 +101,7 @@ class ElsifBranch(VHDLModel_ElsifBranch):
def __init__(
self,
branchNode: Iir,
- condition: Expression,
+ condition: ExpressionUnion,
statements: Iterable[SequentialStatement] = None,
):
super().__init__(condition, statements)
@@ -184,7 +184,7 @@ class IfStatement(VHDLModel_IfStatement, DOMMixin):
@export
class IndexedChoice(VHDLModel_IndexedChoice, DOMMixin):
- def __init__(self, node: Iir, expression: Expression):
+ def __init__(self, node: Iir, expression: ExpressionUnion):
super().__init__(expression)
DOMMixin.__init__(self, node)
@@ -253,7 +253,7 @@ class CaseStatement(VHDLModel_CaseStatement, DOMMixin):
self,
caseNode: Iir,
label: str,
- expression: Expression,
+ expression: ExpressionUnion,
cases: Iterable[SequentialCase],
):
super().__init__(expression, cases, label)
@@ -459,9 +459,9 @@ class SequentialAssertStatement(VHDLModel_SequentialAssertStatement, DOMMixin):
def __init__(
self,
assertNode: Iir,
- condition: Expression,
- message: Expression = None,
- severity: Expression = None,
+ condition: ExpressionUnion,
+ message: ExpressionUnion = None,
+ severity: ExpressionUnion = None,
label: str = None,
):
super().__init__(condition, message, severity, label)
@@ -493,8 +493,8 @@ class SequentialReportStatement(VHDLModel_SequentialReportStatement, DOMMixin):
def __init__(
self,
reportNode: Iir,
- message: Expression,
- severity: Expression = None,
+ message: ExpressionUnion,
+ severity: ExpressionUnion = None,
label: str = None,
):
super().__init__(message, severity, label)
@@ -521,8 +521,8 @@ class WaitStatement(VHDLModel_WaitStatement, DOMMixin):
self,
waitNode: Iir,
sensitivityList: Iterable[Name] = None,
- condition: Expression = None,
- timeout: Expression = None,
+ condition: ExpressionUnion = None,
+ timeout: ExpressionUnion = None,
label: str = None,
):
super().__init__(sensitivityList, condition, timeout, label)