Fixes due to a bug in pyVHDLModel. Name Context was used twice.

10 files changed, 104 insertions, 96 deletions

diff --git a/pyGHDL/dom/Aggregates.py b/pyGHDL/dom/Aggregates.py
index 6ca0734e7..dfaee9a2d 100644
--- a/pyGHDL/dom/Aggregates.py
+++ b/pyGHDL/dom/Aggregates.py
@@ -47,7 +47,7 @@ from pyVHDLModel.SyntaxModel import (
     RangedAggregateElement as VHDLModel_RangedAggregateElement,
     NamedAggregateElement as VHDLModel_NamedAggregateElement,
     OthersAggregateElement as VHDLModel_OthersAggregateElement,
-    Expression,
+    ExpressionUnion,
     Symbol,
 )
 from pyGHDL.libghdl._types import Iir
@@ -59,34 +59,34 @@ __all__ = []
 
 @export
 class SimpleAggregateElement(VHDLModel_SimpleAggregateElement, DOMMixin):
-    def __init__(self, node: Iir, expression: Expression):
+    def __init__(self, node: Iir, expression: ExpressionUnion):
         super().__init__(expression)
         DOMMixin.__init__(self, node)
 
 
 @export
 class IndexedAggregateElement(VHDLModel_IndexedAggregateElement, DOMMixin):
-    def __init__(self, node: Iir, index: Expression, expression: Expression):
+    def __init__(self, node: Iir, index: ExpressionUnion, expression: ExpressionUnion):
         super().__init__(index, expression)
         DOMMixin.__init__(self, node)
 
 
 @export
 class RangedAggregateElement(VHDLModel_RangedAggregateElement, DOMMixin):
-    def __init__(self, node: Iir, rng: Range, expression: Expression):
+    def __init__(self, node: Iir, rng: Range, expression: ExpressionUnion):
         super().__init__(rng, expression)
         DOMMixin.__init__(self, node)
 
 
 @export
 class NamedAggregateElement(VHDLModel_NamedAggregateElement, DOMMixin):
-    def __init__(self, node: Iir, name: Symbol, expression: Expression):
+    def __init__(self, node: Iir, name: Symbol, expression: ExpressionUnion):
         super().__init__(name, expression)
         DOMMixin.__init__(self, node)
 
 
 @export
 class OthersAggregateElement(VHDLModel_OthersAggregateElement, DOMMixin):
-    def __init__(self, node: Iir, expression: Expression):
+    def __init__(self, node: Iir, expression: ExpressionUnion):
         super().__init__(expression)
         DOMMixin.__init__(self, node)
diff --git a/pyGHDL/dom/Concurrent.py b/pyGHDL/dom/Concurrent.py
index a1949c86b..740802d18 100644
--- a/pyGHDL/dom/Concurrent.py
+++ b/pyGHDL/dom/Concurrent.py
@@ -60,7 +60,7 @@ from pyVHDLModel.SyntaxModel import (
     Name,
     ConcurrentStatement,
     SequentialStatement,
-    Expression,
+    ExpressionUnion,
     ConcurrentChoice,
     ConcurrentCase,
     AssociationItem,
@@ -74,21 +74,27 @@ from pyGHDL.dom._Utils import GetNameOfNode
 
 @export
 class GenericAssociationItem(VHDLModel_GenericAssociationItem, DOMMixin):
-    def __init__(self, associationNode: Iir, actual: Expression, formal: Name = None):
+    def __init__(
+        self, associationNode: Iir, actual: ExpressionUnion, formal: Name = None
+    ):
         super().__init__(actual, formal)
         DOMMixin.__init__(self, associationNode)
 
 
 @export
 class PortAssociationItem(VHDLModel_PortAssociationItem, DOMMixin):
-    def __init__(self, associationNode: Iir, actual: Expression, formal: Name = None):
+    def __init__(
+        self, associationNode: Iir, actual: ExpressionUnion, formal: Name = None
+    ):
         super().__init__(actual, formal)
         DOMMixin.__init__(self, associationNode)
 
 
 @export
 class ParameterAssociationItem(VHDLModel_ParameterAssociationItem, DOMMixin):
-    def __init__(self, associationNode: Iir, actual: Expression, formal: Name = None):
+    def __init__(
+        self, associationNode: Iir, actual: ExpressionUnion, formal: Name = None
+    ):
         super().__init__(actual, formal)
         DOMMixin.__init__(self, associationNode)
 
@@ -303,7 +309,7 @@ class IfGenerateBranch(VHDLModel_IfGenerateBranch):
     def __init__(
         self,
         branchNode: Iir,
-        condition: Expression,
+        condition: ExpressionUnion,
         declaredItems: Iterable = None,
         statements: Iterable[ConcurrentStatement] = None,
         alternativeLabel: str = None,
@@ -344,7 +350,7 @@ class ElsifGenerateBranch(VHDLModel_ElsifGenerateBranch):
     def __init__(
         self,
         branchNode: Iir,
-        condition: Expression,
+        condition: ExpressionUnion,
         declaredItems: Iterable = None,
         statements: Iterable[ConcurrentStatement] = None,
         alternativeLabel: str = None,
@@ -455,7 +461,7 @@ class IfGenerateStatement(VHDLModel_IfGenerateStatement, DOMMixin):
 
 @export
 class IndexedGenerateChoice(VHDLModel_IndexedGenerateChoice, DOMMixin):
-    def __init__(self, node: Iir, expression: Expression):
+    def __init__(self, node: Iir, expression: ExpressionUnion):
         super().__init__(expression)
         DOMMixin.__init__(self, node)
 
@@ -552,7 +558,7 @@ class CaseGenerateStatement(VHDLModel_CaseGenerateStatement, DOMMixin):
         self,
         generateNode: Iir,
         label: str,
-        expression: Expression,
+        expression: ExpressionUnion,
         cases: Iterable[ConcurrentCase],
     ):
         super().__init__(label, expression, cases)
@@ -706,7 +712,9 @@ class ForGenerateStatement(VHDLModel_ForGenerateStatement, DOMMixin):
 
 @export
 class WaveformElement(VHDLModel_WaveformElement, DOMMixin):
-    def __init__(self, waveNode: Iir, expression: Expression, after: Expression):
+    def __init__(
+        self, waveNode: Iir, expression: ExpressionUnion, after: ExpressionUnion
+    ):
         super().__init__(expression, after)
         DOMMixin.__init__(self, waveNode)
 
diff --git a/pyGHDL/dom/DesignUnit.py b/pyGHDL/dom/DesignUnit.py
index ff738e7dc..3fe8f74bf 100644
--- a/pyGHDL/dom/DesignUnit.py
+++ b/pyGHDL/dom/DesignUnit.py
@@ -43,6 +43,7 @@ from typing import Iterable
 
 from pydecor import export
 
+from pyVHDLModel import ContextUnion, EntityOrSymbol
 from pyVHDLModel.SyntaxModel import (
     LibraryClause as VHDLModel_LibraryClause,
     UseClause as VHDLModel_UseClause,
@@ -57,7 +58,6 @@ from pyVHDLModel.SyntaxModel import (
     Component as VHDLModel_Component,
     GenericInterfaceItem,
     PortInterfaceItem,
-    EntityOrSymbol,
     Name,
     ConcurrentStatement,
 )
@@ -127,7 +127,7 @@ class Entity(VHDLModel_Entity, DOMMixin):
         self,
         node: Iir,
         identifier: str,
-        contextItems: Iterable[Context] = None,
+        contextItems: Iterable[ContextUnion] = None,
         genericItems: Iterable[GenericInterfaceItem] = None,
         portItems: Iterable[PortInterfaceItem] = None,
         declaredItems: Iterable = None,
@@ -139,7 +139,7 @@ class Entity(VHDLModel_Entity, DOMMixin):
         DOMMixin.__init__(self, node)
 
     @classmethod
-    def parse(cls, entityNode: Iir, contextItems: Iterable[Context]):
+    def parse(cls, entityNode: Iir, contextItems: Iterable[ContextUnion]):
         name = GetNameOfNode(entityNode)
         generics = GetGenericsFromChainedNodes(nodes.Get_Generic_Chain(entityNode))
         ports = GetPortsFromChainedNodes(nodes.Get_Port_Chain(entityNode))
@@ -164,7 +164,7 @@ class Architecture(VHDLModel_Architecture, DOMMixin):
         node: Iir,
         identifier: str,
         entity: EntityOrSymbol,
-        contextItems: Iterable[Context] = None,
+        contextItems: Iterable[ContextUnion] = None,
         declaredItems: Iterable = None,
         statements: Iterable["ConcurrentStatement"] = None,
     ):
@@ -172,7 +172,7 @@ class Architecture(VHDLModel_Architecture, DOMMixin):
         DOMMixin.__init__(self, node)
 
     @classmethod
-    def parse(cls, architectureNode: Iir, contextItems: Iterable[Context]):
+    def parse(cls, architectureNode: Iir, contextItems: Iterable[ContextUnion]):
         name = GetNameOfNode(architectureNode)
         entityNameNode = nodes.Get_Entity_Name(architectureNode)
         entityName = GetNameOfNode(entityNameNode)
@@ -218,7 +218,7 @@ class Package(VHDLModel_Package, DOMMixin):
         self,
         node: Iir,
         identifier: str,
-        contextItems: Iterable[Context] = None,
+        contextItems: Iterable[ContextUnion] = None,
         genericItems: Iterable[GenericInterfaceItem] = None,
         declaredItems: Iterable = None,
     ):
@@ -226,7 +226,7 @@ class Package(VHDLModel_Package, DOMMixin):
         DOMMixin.__init__(self, node)
 
     @classmethod
-    def parse(cls, packageNode: Iir, contextItems: Iterable[Context]):
+    def parse(cls, packageNode: Iir, contextItems: Iterable[ContextUnion]):
         name = GetNameOfNode(packageNode)
 
         packageHeader = nodes.Get_Package_Header(packageNode)
@@ -252,14 +252,14 @@ class PackageBody(VHDLModel_PackageBody, DOMMixin):
         self,
         node: Iir,
         identifier: str,
-        contextItems: Iterable[Context] = None,
+        contextItems: Iterable[ContextUnion] = None,
         declaredItems: Iterable = None,
     ):
         super().__init__(identifier, contextItems, declaredItems)
         DOMMixin.__init__(self, node)
 
     @classmethod
-    def parse(cls, packageBodyNode: Iir, contextItems: Iterable[Context]):
+    def parse(cls, packageBodyNode: Iir, contextItems: Iterable[ContextUnion]):
         name = GetNameOfNode(packageBodyNode)
         declaredItems = GetDeclaredItemsFromChainedNodes(
             nodes.Get_Declaration_Chain(packageBodyNode), "package", name
diff --git a/pyGHDL/dom/Expression.py b/pyGHDL/dom/Expression.py
index 3769b9fb6..ce5945d46 100644
--- a/pyGHDL/dom/Expression.py
+++ b/pyGHDL/dom/Expression.py
@@ -83,7 +83,7 @@ from pyVHDLModel.SyntaxModel import (
     SubtypeAllocation as VHDLModel_SubtypeAllocation,
     QualifiedExpressionAllocation as VHDLModel_QualifiedExpressionAllocation,
     Aggregate as VHDLModel_Aggregate,
-    Expression,
+    ExpressionUnion,
     AggregateElement,
     SubtypeOrSymbol,
     Symbol,
@@ -130,7 +130,7 @@ class _ParseBinaryExpressionMixin:
 class InverseExpression(
     VHDLModel_InverseExpression, DOMMixin, _ParseUnaryExpressionMixin
 ):
-    def __init__(self, node: Iir, operand: Expression):
+    def __init__(self, node: Iir, operand: ExpressionUnion):
         super().__init__(operand)
         DOMMixin.__init__(self, node)
 
@@ -139,7 +139,7 @@ class InverseExpression(
 class IdentityExpression(
     VHDLModel_IdentityExpression, DOMMixin, _ParseUnaryExpressionMixin
 ):
-    def __init__(self, node: Iir, operand: Expression):
+    def __init__(self, node: Iir, operand: ExpressionUnion):
         super().__init__(operand)
         DOMMixin.__init__(self, node)
 
@@ -148,7 +148,7 @@ class IdentityExpression(
 class NegationExpression(
     VHDLModel_NegationExpression, DOMMixin, _ParseUnaryExpressionMixin
 ):
-    def __init__(self, node: Iir, operand: Expression):
+    def __init__(self, node: Iir, operand: ExpressionUnion):
         super().__init__(operand)
         DOMMixin.__init__(self, node)
 
@@ -157,7 +157,7 @@ class NegationExpression(
 class AbsoluteExpression(
     VHDLModel_AbsoluteExpression, DOMMixin, _ParseUnaryExpressionMixin
 ):
-    def __init__(self, node: Iir, operand: Expression):
+    def __init__(self, node: Iir, operand: ExpressionUnion):
         super().__init__(operand)
         DOMMixin.__init__(self, node)
 
@@ -166,7 +166,7 @@ class AbsoluteExpression(
 class ParenthesisExpression(
     VHDLModel_ParenthesisExpression, DOMMixin, _ParseUnaryExpressionMixin
 ):
-    def __init__(self, node: Iir, operand: Expression):
+    def __init__(self, node: Iir, operand: ExpressionUnion):
         super().__init__(operand)
         DOMMixin.__init__(self, node)
 
@@ -180,14 +180,14 @@ class ParenthesisExpression(
 
 @export
 class TypeConversion(VHDLModel_TypeConversion, DOMMixin):
-    def __init__(self, node: Iir, operand: Expression):
+    def __init__(self, node: Iir, operand: ExpressionUnion):
         super().__init__(operand)
         DOMMixin.__init__(self, node)
 
 
 @export
 class FunctionCall(VHDLModel_FunctionCall, DOMMixin):
-    def __init__(self, node: Iir, operand: Expression):
+    def __init__(self, node: Iir, operand: ExpressionUnion):
         super().__init__()
         DOMMixin.__init__(self, node)
 
@@ -211,14 +211,14 @@ class RangeExpression(VHDLModel_RangeExpression, DOMMixin):
 
 @export
 class AscendingRangeExpression(VHDLModel_AscendingRangeExpression, DOMMixin):
-    def __init__(self, node: Iir, left: Expression, right: Expression):
+    def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion):
         super().__init__(left, right)
         DOMMixin.__init__(self, node)
 
 
 @export
 class DescendingRangeExpression(VHDLModel_DescendingRangeExpression, DOMMixin):
-    def __init__(self, node: Iir, left: Expression, right: Expression):
+    def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion):
         super().__init__(left, right)
         DOMMixin.__init__(self, node)
 
@@ -227,7 +227,7 @@ class DescendingRangeExpression(VHDLModel_DescendingRangeExpression, DOMMixin):
 class AdditionExpression(
     VHDLModel_AdditionExpression, DOMMixin, _ParseBinaryExpressionMixin
 ):
-    def __init__(self, node: Iir, left: Expression, right: Expression):
+    def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion):
         super().__init__(left, right)
         DOMMixin.__init__(self, node)
 
@@ -236,7 +236,7 @@ class AdditionExpression(
 class SubtractionExpression(
     VHDLModel_SubtractionExpression, DOMMixin, _ParseBinaryExpressionMixin
 ):
-    def __init__(self, node: Iir, left: Expression, right: Expression):
+    def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion):
         super().__init__(left, right)
         DOMMixin.__init__(self, node)
 
@@ -245,7 +245,7 @@ class SubtractionExpression(
 class ConcatenationExpression(
     VHDLModel_ConcatenationExpression, DOMMixin, _ParseBinaryExpressionMixin
 ):
-    def __init__(self, node: Iir, left: Expression, right: Expression):
+    def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion):
         super().__init__(left, right)
         DOMMixin.__init__(self, node)
 
@@ -254,7 +254,7 @@ class ConcatenationExpression(
 class MultiplyExpression(
     VHDLModel_MultiplyExpression, DOMMixin, _ParseBinaryExpressionMixin
 ):
-    def __init__(self, node: Iir, left: Expression, right: Expression):
+    def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion):
         super().__init__(left, right)
         DOMMixin.__init__(self, node)
 
@@ -263,7 +263,7 @@ class MultiplyExpression(
 class DivisionExpression(
     VHDLModel_DivisionExpression, DOMMixin, _ParseBinaryExpressionMixin
 ):
-    def __init__(self, node: Iir, left: Expression, right: Expression):
+    def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion):
         super().__init__(left, right)
         DOMMixin.__init__(self, node)
 
@@ -272,7 +272,7 @@ class DivisionExpression(
 class RemainderExpression(
     VHDLModel_RemainderExpression, DOMMixin, _ParseBinaryExpressionMixin
 ):
-    def __init__(self, node: Iir, left: Expression, right: Expression):
+    def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion):
         super().__init__(left, right)
         DOMMixin.__init__(self, node)
 
@@ -281,7 +281,7 @@ class RemainderExpression(
 class ModuloExpression(
     VHDLModel_ModuloExpression, DOMMixin, _ParseBinaryExpressionMixin
 ):
-    def __init__(self, node: Iir, left: Expression, right: Expression):
+    def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion):
         super().__init__(left, right)
         DOMMixin.__init__(self, node)
 
@@ -290,56 +290,56 @@ class ModuloExpression(
 class ExponentiationExpression(
     VHDLModel_ExponentiationExpression, DOMMixin, _ParseBinaryExpressionMixin
 ):
-    def __init__(self, node: Iir, left: Expression, right: Expression):
+    def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion):
         super().__init__(left, right)
         DOMMixin.__init__(self, node)
 
 
 @export
 class AndExpression(VHDLModel_AndExpression, DOMMixin, _ParseBinaryExpressionMixin):
-    def __init__(self, node: Iir, left: Expression, right: Expression):
+    def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion):
         super().__init__(left, right)
         DOMMixin.__init__(self, node)
 
 
 @export
 class NandExpression(VHDLModel_NandExpression, DOMMixin, _ParseBinaryExpressionMixin):
-    def __init__(self, node: Iir, left: Expression, right: Expression):
+    def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion):
         super().__init__(left, right)
         DOMMixin.__init__(self, node)
 
 
 @export
 class OrExpression(VHDLModel_OrExpression, DOMMixin, _ParseBinaryExpressionMixin):
-    def __init__(self, node: Iir, left: Expression, right: Expression):
+    def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion):
         super().__init__(left, right)
         DOMMixin.__init__(self, node)
 
 
 @export
 class NorExpression(VHDLModel_NorExpression, DOMMixin, _ParseBinaryExpressionMixin):
-    def __init__(self, node: Iir, left: Expression, right: Expression):
+    def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion):
         super().__init__(left, right)
         DOMMixin.__init__(self, node)
 
 
 @export
 class XorExpression(VHDLModel_XorExpression, DOMMixin, _ParseBinaryExpressionMixin):
-    def __init__(self, node: Iir, left: Expression, right: Expression):
+    def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion):
         super().__init__(left, right)
         DOMMixin.__init__(self, node)
 
 
 @export
 class XnorExpression(VHDLModel_XnorExpression, DOMMixin, _ParseBinaryExpressionMixin):
-    def __init__(self, node: Iir, left: Expression, right: Expression):
+    def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion):
         super().__init__(left, right)
         DOMMixin.__init__(self, node)
 
 
 @export
 class EqualExpression(VHDLModel_EqualExpression, DOMMixin, _ParseBinaryExpressionMixin):
-    def __init__(self, node: Iir, left: Expression, right: Expression):
+    def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion):
         super().__init__(left, right)
         DOMMixin.__init__(self, node)
 
@@ -348,7 +348,7 @@ class EqualExpression(VHDLModel_EqualExpression, DOMMixin, _ParseBinaryExpressio
 class UnequalExpression(
     VHDLModel_UnequalExpression, DOMMixin, _ParseBinaryExpressionMixin
 ):
-    def __init__(self, node: Iir, left: Expression, right: Expression):
+    def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion):
         super().__init__(left, right)
         DOMMixin.__init__(self, node)
 
@@ -357,7 +357,7 @@ class UnequalExpression(
 class LessThanExpression(
     VHDLModel_LessThanExpression, DOMMixin, _ParseBinaryExpressionMixin
 ):
-    def __init__(self, node: Iir, left: Expression, right: Expression):
+    def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion):
         super().__init__(left, right)
         DOMMixin.__init__(self, node)
 
@@ -366,7 +366,7 @@ class LessThanExpression(
 class LessEqualExpression(
     VHDLModel_LessEqualExpression, DOMMixin, _ParseBinaryExpressionMixin
 ):
-    def __init__(self, node: Iir, left: Expression, right: Expression):
+    def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion):
         super().__init__(left, right)
         DOMMixin.__init__(self, node)
 
@@ -375,7 +375,7 @@ class LessEqualExpression(
 class GreaterThanExpression(
     VHDLModel_GreaterThanExpression, DOMMixin, _ParseBinaryExpressionMixin
 ):
-    def __init__(self, node: Iir, left: Expression, right: Expression):
+    def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion):
         super().__init__(left, right)
         DOMMixin.__init__(self, node)
 
@@ -384,7 +384,7 @@ class GreaterThanExpression(
 class GreaterEqualExpression(
     VHDLModel_GreaterEqualExpression, DOMMixin, _ParseBinaryExpressionMixin
 ):
-    def __init__(self, node: Iir, left: Expression, right: Expression):
+    def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion):
         super().__init__(left, right)
         DOMMixin.__init__(self, node)
 
@@ -393,7 +393,7 @@ class GreaterEqualExpression(
 class MatchingEqualExpression(
     VHDLModel_MatchingEqualExpression, DOMMixin, _ParseBinaryExpressionMixin
 ):
-    def __init__(self, node: Iir, left: Expression, right: Expression):
+    def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion):
         super().__init__(left, right)
         DOMMixin.__init__(self, node)
 
@@ -402,7 +402,7 @@ class MatchingEqualExpression(
 class MatchingUnequalExpression(
     VHDLModel_MatchingUnequalExpression, DOMMixin, _ParseBinaryExpressionMixin
 ):
-    def __init__(self, node: Iir, left: Expression, right: Expression):
+    def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion):
         super().__init__(left, right)
         DOMMixin.__init__(self, node)
 
@@ -411,7 +411,7 @@ class MatchingUnequalExpression(
 class MatchingLessThanExpression(
     VHDLModel_MatchingLessThanExpression, DOMMixin, _ParseBinaryExpressionMixin
 ):
-    def __init__(self, node: Iir, left: Expression, right: Expression):
+    def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion):
         super().__init__(left, right)
         DOMMixin.__init__(self, node)
 
@@ -420,7 +420,7 @@ class MatchingLessThanExpression(
 class MatchingLessEqualExpression(
     VHDLModel_MatchingLessEqualExpression, DOMMixin, _ParseBinaryExpressionMixin
 ):
-    def __init__(self, node: Iir, left: Expression, right: Expression):
+    def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion):
         super().__init__(left, right)
         DOMMixin.__init__(self, node)
 
@@ -429,7 +429,7 @@ class MatchingLessEqualExpression(
 class MatchingGreaterThanExpression(
     VHDLModel_MatchingGreaterThanExpression, DOMMixin, _ParseBinaryExpressionMixin
 ):
-    def __init__(self, node: Iir, left: Expression, right: Expression):
+    def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion):
         super().__init__(left, right)
         DOMMixin.__init__(self, node)
 
@@ -438,7 +438,7 @@ class MatchingGreaterThanExpression(
 class MatchingGreaterEqualExpression(
     VHDLModel_MatchingGreaterEqualExpression, DOMMixin, _ParseBinaryExpressionMixin
 ):
-    def __init__(self, node: Iir, left: Expression, right: Expression):
+    def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion):
         super().__init__(left, right)
         DOMMixin.__init__(self, node)
 
@@ -447,7 +447,7 @@ class MatchingGreaterEqualExpression(
 class ShiftRightLogicExpression(
     VHDLModel_ShiftRightLogicExpression, DOMMixin, _ParseBinaryExpressionMixin
 ):
-    def __init__(self, node: Iir, left: Expression, right: Expression):
+    def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion):
         super().__init__(left, right)
         DOMMixin.__init__(self, node)
 
@@ -456,7 +456,7 @@ class ShiftRightLogicExpression(
 class ShiftLeftLogicExpression(
     VHDLModel_ShiftLeftLogicExpression, DOMMixin, _ParseBinaryExpressionMixin
 ):
-    def __init__(self, node: Iir, left: Expression, right: Expression):
+    def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion):
         super().__init__(left, right)
         DOMMixin.__init__(self, node)
 
@@ -465,7 +465,7 @@ class ShiftLeftLogicExpression(
 class ShiftRightArithmeticExpression(
     VHDLModel_ShiftRightArithmeticExpression, DOMMixin, _ParseBinaryExpressionMixin
 ):
-    def __init__(self, node: Iir, left: Expression, right: Expression):
+    def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion):
         super().__init__(left, right)
         DOMMixin.__init__(self, node)
 
@@ -474,7 +474,7 @@ class ShiftRightArithmeticExpression(
 class ShiftLeftArithmeticExpression(
     VHDLModel_ShiftLeftArithmeticExpression, DOMMixin, _ParseBinaryExpressionMixin
 ):
-    def __init__(self, node: Iir, left: Expression, right: Expression):
+    def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion):
         super().__init__(left, right)
         DOMMixin.__init__(self, node)
 
@@ -483,7 +483,7 @@ class ShiftLeftArithmeticExpression(
 class RotateRightExpression(
     VHDLModel_RotateRightExpression, DOMMixin, _ParseBinaryExpressionMixin
 ):
-    def __init__(self, node: Iir, left: Expression, right: Expression):
+    def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion):
         super().__init__(left, right)
         DOMMixin.__init__(self, node)
 
@@ -492,14 +492,14 @@ class RotateRightExpression(
 class RotateLeftExpression(
     VHDLModel_RotateLeftExpression, DOMMixin, _ParseBinaryExpressionMixin
 ):
-    def __init__(self, node: Iir, left: Expression, right: Expression):
+    def __init__(self, node: Iir, left: ExpressionUnion, right: ExpressionUnion):
         super().__init__(left, right)
         DOMMixin.__init__(self, node)
 
 
 @export
 class QualifiedExpression(VHDLModel_QualifiedExpression, DOMMixin):
-    def __init__(self, node: Iir, subtype: SubtypeOrSymbol, operand: Expression):
+    def __init__(self, node: Iir, subtype: SubtypeOrSymbol, operand: ExpressionUnion):
         super().__init__(subtype, operand)
         DOMMixin.__init__(self, node)
 
diff --git a/pyGHDL/dom/InterfaceItem.py b/pyGHDL/dom/InterfaceItem.py
index 3a9c7238f..af1b681cd 100644
--- a/pyGHDL/dom/InterfaceItem.py
+++ b/pyGHDL/dom/InterfaceItem.py
@@ -47,7 +47,7 @@ from pyVHDLModel.SyntaxModel import (
     ParameterFileInterfaceItem as VHDLModel_ParameterFileInterfaceItem,
     Mode,
     SubtypeOrSymbol,
-    Expression,
+    ExpressionUnion,
 )
 
 from pyGHDL.libghdl._types import Iir
@@ -68,7 +68,7 @@ class GenericConstantInterfaceItem(VHDLModel_GenericConstantInterfaceItem, DOMMi
         identifiers: List[str],
         mode: Mode,
         subtype: SubtypeOrSymbol,
-        defaultExpression: Expression,
+        defaultExpression: ExpressionUnion,
     ):
         super().__init__(identifiers, mode, subtype, defaultExpression)
         DOMMixin.__init__(self, node)
@@ -168,7 +168,7 @@ class PortSignalInterfaceItem(VHDLModel_PortSignalInterfaceItem, DOMMixin):
         identifiers: List[str],
         mode: Mode,
         subtype: SubtypeOrSymbol,
-        defaultExpression: Expression = None,
+        defaultExpression: ExpressionUnion = None,
     ):
         super().__init__(identifiers, mode, subtype, defaultExpression)
         DOMMixin.__init__(self, node)
@@ -207,7 +207,7 @@ class ParameterConstantInterfaceItem(
         identifiers: List[str],
         mode: Mode,
         subtype: SubtypeOrSymbol,
-        defaultExpression: Expression = None,
+        defaultExpression: ExpressionUnion = None,
     ):
         super().__init__(identifiers, mode, subtype, defaultExpression)
         DOMMixin.__init__(self, node)
@@ -248,7 +248,7 @@ class ParameterVariableInterfaceItem(
         identifiers: List[str],
         mode: Mode,
         subtype: SubtypeOrSymbol,
-        defaultExpression: Expression = None,
+        defaultExpression: ExpressionUnion = None,
     ):
         super().__init__(identifiers, mode, subtype, defaultExpression)
         DOMMixin.__init__(self, node)
@@ -287,7 +287,7 @@ class ParameterSignalInterfaceItem(VHDLModel_ParameterSignalInterfaceItem, DOMMi
         identifiers: List[str],
         mode: Mode,
         subtype: SubtypeOrSymbol,
-        defaultExpression: Expression = None,
+        defaultExpression: ExpressionUnion = None,
     ):
         super().__init__(identifiers, mode, subtype, defaultExpression)
         DOMMixin.__init__(self, node)
diff --git a/pyGHDL/dom/Object.py b/pyGHDL/dom/Object.py
index b83f352a4..def09d50c 100644
--- a/pyGHDL/dom/Object.py
+++ b/pyGHDL/dom/Object.py
@@ -41,7 +41,7 @@ from pyVHDLModel.SyntaxModel import (
     SharedVariable as VHDLModel_SharedVariable,
     Signal as VHDLModel_Signal,
     File as VHDLModel_File,
-    Expression,
+    ExpressionUnion,
     SubtypeOrSymbol,
 )
 
@@ -60,7 +60,7 @@ class Constant(VHDLModel_Constant, DOMMixin):
         node: Iir,
         identifiers: List[str],
         subtype: SubtypeOrSymbol,
-        defaultExpression: Expression,
+        defaultExpression: ExpressionUnion,
     ):
         super().__init__(identifiers, subtype, defaultExpression)
         DOMMixin.__init__(self, node)
@@ -127,7 +127,7 @@ class Variable(VHDLModel_Variable, DOMMixin):
         node: Iir,
         identifiers: List[str],
         subtype: SubtypeOrSymbol,
-        defaultExpression: Expression,
+        defaultExpression: ExpressionUnion,
     ):
         super().__init__(identifiers, subtype, defaultExpression)
         DOMMixin.__init__(self, node)
@@ -185,7 +185,7 @@ class Signal(VHDLModel_Signal, DOMMixin):
         node: Iir,
         identifiers: List[str],
         subtype: SubtypeOrSymbol,
-        defaultExpression: Expression,
+        defaultExpression: ExpressionUnion,
     ):
         super().__init__(identifiers, subtype, defaultExpression)
         DOMMixin.__init__(self, node)
diff --git a/pyGHDL/dom/Sequential.py b/pyGHDL/dom/Sequential.py
index 4f511c16f..be4793b2a 100644
--- a/pyGHDL/dom/Sequential.py
+++ b/pyGHDL/dom/Sequential.py
@@ -57,7 +57,7 @@ from pyVHDLModel.SyntaxModel import (
     WaitStatement as VHDLModel_WaitStatement,
     Name,
     SequentialStatement,
-    Expression,
+    ExpressionUnion,
     SequentialChoice,
     SequentialCase,
 )
@@ -74,7 +74,7 @@ class IfBranch(VHDLModel_IfBranch):
     def __init__(
         self,
         branchNode: Iir,
-        condition: Expression,
+        condition: ExpressionUnion,
         statements: Iterable[SequentialStatement] = None,
     ):
         super().__init__(condition, statements)
@@ -101,7 +101,7 @@ class ElsifBranch(VHDLModel_ElsifBranch):
     def __init__(
         self,
         branchNode: Iir,
-        condition: Expression,
+        condition: ExpressionUnion,
         statements: Iterable[SequentialStatement] = None,
     ):
         super().__init__(condition, statements)
@@ -184,7 +184,7 @@ class IfStatement(VHDLModel_IfStatement, DOMMixin):
 
 @export
 class IndexedChoice(VHDLModel_IndexedChoice, DOMMixin):
-    def __init__(self, node: Iir, expression: Expression):
+    def __init__(self, node: Iir, expression: ExpressionUnion):
         super().__init__(expression)
         DOMMixin.__init__(self, node)
 
@@ -253,7 +253,7 @@ class CaseStatement(VHDLModel_CaseStatement, DOMMixin):
         self,
         caseNode: Iir,
         label: str,
-        expression: Expression,
+        expression: ExpressionUnion,
         cases: Iterable[SequentialCase],
     ):
         super().__init__(expression, cases, label)
@@ -459,9 +459,9 @@ class SequentialAssertStatement(VHDLModel_SequentialAssertStatement, DOMMixin):
     def __init__(
         self,
         assertNode: Iir,
-        condition: Expression,
-        message: Expression = None,
-        severity: Expression = None,
+        condition: ExpressionUnion,
+        message: ExpressionUnion = None,
+        severity: ExpressionUnion = None,
         label: str = None,
     ):
         super().__init__(condition, message, severity, label)
@@ -493,8 +493,8 @@ class SequentialReportStatement(VHDLModel_SequentialReportStatement, DOMMixin):
     def __init__(
         self,
         reportNode: Iir,
-        message: Expression,
-        severity: Expression = None,
+        message: ExpressionUnion,
+        severity: ExpressionUnion = None,
         label: str = None,
     ):
         super().__init__(message, severity, label)
@@ -521,8 +521,8 @@ class WaitStatement(VHDLModel_WaitStatement, DOMMixin):
         self,
         waitNode: Iir,
         sensitivityList: Iterable[Name] = None,
-        condition: Expression = None,
-        timeout: Expression = None,
+        condition: ExpressionUnion = None,
+        timeout: ExpressionUnion = None,
         label: str = None,
     ):
         super().__init__(sensitivityList, condition, timeout, label)
diff --git a/pyGHDL/dom/Symbol.py b/pyGHDL/dom/Symbol.py
index 931fc82f2..f52afbb18 100644
--- a/pyGHDL/dom/Symbol.py
+++ b/pyGHDL/dom/Symbol.py
@@ -41,7 +41,7 @@ from pyVHDLModel.SyntaxModel import (
     ConstrainedCompositeSubtypeSymbol as VHDLModel_ConstrainedCompositeSubtypeSymbol,
     SimpleObjectOrFunctionCallSymbol as VHDLModel_SimpleObjectOrFunctionCallSymbol,
     IndexedObjectOrFunctionCallSymbol as VHDLModel_IndexedObjectOrFunctionCallSymbol,
-    Constraint,
+    ConstraintUnion,
     Name,
 )
 from pyGHDL.libghdl._types import Iir
@@ -87,7 +87,7 @@ class ConstrainedCompositeSubtypeSymbol(
     VHDLModel_ConstrainedCompositeSubtypeSymbol, DOMMixin
 ):
     def __init__(
-        self, node: Iir, subtypeName: Name, constraints: List[Constraint] = None
+        self, node: Iir, subtypeName: Name, constraints: List[ConstraintUnion] = None
     ):
         super().__init__(subtypeName, constraints)
         DOMMixin.__init__(self, node)
diff --git a/pyGHDL/dom/_Translate.py b/pyGHDL/dom/_Translate.py
index 626ffd3fa..d64e38d82 100644
--- a/pyGHDL/dom/_Translate.py
+++ b/pyGHDL/dom/_Translate.py
@@ -44,9 +44,9 @@ from pyGHDL.dom.Sequential import (
     SequentialSimpleSignalAssignment,
 )
 from pyVHDLModel.SyntaxModel import (
-    Constraint,
+    ConstraintUnion,
     Direction,
-    Expression,
+    ExpressionUnion,
     SubtypeOrSymbol,
     BaseType,
     GenericInterfaceItem,
@@ -225,7 +225,7 @@ def GetAssociations(node: Iir) -> List:
 @export
 def GetArrayConstraintsFromSubtypeIndication(
     subtypeIndication: Iir,
-) -> List[Constraint]:
+) -> List[ConstraintUnion]:
     constraints = []
     for constraint in utils.flist_iter(
         nodes.Get_Index_Constraint_List(subtypeIndication)
@@ -467,7 +467,7 @@ __EXPRESSION_TRANSLATION = {
 
 
 @export
-def GetExpressionFromNode(node: Iir) -> Expression:
+def GetExpressionFromNode(node: Iir) -> ExpressionUnion:
     kind = GetIirKindOfNode(node)
 
     try:
diff --git a/pyGHDL/dom/requirements.txt b/pyGHDL/dom/requirements.txt
index ea7731edc..d296f0e96 100644
--- a/pyGHDL/dom/requirements.txt
+++ b/pyGHDL/dom/requirements.txt
@@ -1,4 +1,4 @@
 -r ../libghdl/requirements.txt
 
-pyVHDLModel==0.11.4
+pyVHDLModel==0.11.5
 #https://github.com/VHDL/pyVHDLModel/archive/dev.zip#pyVHDLModel