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authorPatrick Lehmann <Patrick.Lehmann@plc2.de>2021-07-26 00:13:11 +0200
committerumarcor <unai.martinezcorral@ehu.eus>2021-08-23 16:35:31 +0200
commitca39821dc013a877a8dbdfabbc3b861eb4d4d2e3 (patch)
treeb731d3bddd9c8e3e7b288de088ad54510b6085ba /pyGHDL/dom/Range.py
parent9df82e519d7e93168d43fb414c48c9e547b0c306 (diff)
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Adjusted to renaming in pyVHDLModel.
Diffstat (limited to 'pyGHDL/dom/Range.py')
-rw-r--r--pyGHDL/dom/Range.py7
1 files changed, 1 insertions, 6 deletions
diff --git a/pyGHDL/dom/Range.py b/pyGHDL/dom/Range.py
index ce8dfbc40..f5153e67d 100644
--- a/pyGHDL/dom/Range.py
+++ b/pyGHDL/dom/Range.py
@@ -32,12 +32,7 @@
# ============================================================================
from pydecor import export
-from pyVHDLModel.VHDLModel import (
- Range as VHDLModel_Range,
- RangeExpression as VHDLModel_RangeExpression,
- Direction,
- Expression,
-)
+from pyVHDLModel.SyntaxModel import Range as VHDLModel_Range
__all__ = []