Adjusted to renaming in pyVHDLModel.

20 files changed, 121 insertions, 63 deletions

diff --git a/pyGHDL/dom/Aggregates.py b/pyGHDL/dom/Aggregates.py
index 87bc44360..6ca0734e7 100644
--- a/pyGHDL/dom/Aggregates.py
+++ b/pyGHDL/dom/Aggregates.py
@@ -9,7 +9,7 @@
 # Authors:
 #   Patrick Lehmann
 #
-# Package module:   DOM: VHDL design units (e.g. context or package).
+# Package module:   DOM: Aggregates.
 #
 # License:
 # ============================================================================
@@ -41,7 +41,7 @@ This module contains all DOM classes for VHDL's design units (:class:`context <E
 """
 from pydecor import export
 
-from pyVHDLModel.VHDLModel import (
+from pyVHDLModel.SyntaxModel import (
     SimpleAggregateElement as VHDLModel_SimpleAggregateElement,
     IndexedAggregateElement as VHDLModel_IndexedAggregateElement,
     RangedAggregateElement as VHDLModel_RangedAggregateElement,
diff --git a/pyGHDL/dom/Attribute.py b/pyGHDL/dom/Attribute.py
index 270f8feb3..97a01f65a 100644
--- a/pyGHDL/dom/Attribute.py
+++ b/pyGHDL/dom/Attribute.py
@@ -9,7 +9,7 @@
 # Authors:
 #   Patrick Lehmann
 #
-# Package module:   DOM: Interface items (e.g. generic or port)
+# Package module:   DOM: Attributes.
 #
 # License:
 # ============================================================================
@@ -34,7 +34,7 @@ from typing import List
 
 from pydecor import export
 
-from pyVHDLModel.VHDLModel import (
+from pyVHDLModel.SyntaxModel import (
     Attribute as VHDLModel_Attribute,
     AttributeSpecification as VHDLModel_AttributeSpecification,
     Name,
diff --git a/pyGHDL/dom/DesignUnit.py b/pyGHDL/dom/DesignUnit.py
index d5bf161fd..13e197075 100644
--- a/pyGHDL/dom/DesignUnit.py
+++ b/pyGHDL/dom/DesignUnit.py
@@ -43,7 +43,7 @@ from typing import List
 
 from pydecor import export
 
-from pyVHDLModel.VHDLModel import (
+from pyVHDLModel.SyntaxModel import (
     UseClause as VHDLModel_UseClause,
     Entity as VHDLModel_Entity,
     Architecture as VHDLModel_Architecture,
diff --git a/pyGHDL/dom/Expression.py b/pyGHDL/dom/Expression.py
index 972b86ced..83a3f65df 100644
--- a/pyGHDL/dom/Expression.py
+++ b/pyGHDL/dom/Expression.py
@@ -9,7 +9,7 @@
 # Authors:
 #   Patrick Lehmann
 #
-# Package module:   DOM: Interface items (e.g. generic or port)
+# Package module:   DOM: Expressions.
 #
 # License:
 # ============================================================================
@@ -34,8 +34,7 @@ from typing import List, Union
 
 from pydecor import export
 
-from pyGHDL.dom import DOMMixin, DOMException
-from pyVHDLModel.VHDLModel import (
+from pyVHDLModel.SyntaxModel import (
     UnaryExpression as VHDLModel_UnaryExpression,
     BinaryExpression as VHDLModel_BinaryExpression,
     InverseExpression as VHDLModel_InverseExpression,
@@ -93,6 +92,7 @@ from pyVHDLModel.VHDLModel import (
 from pyGHDL.libghdl import utils
 from pyGHDL.libghdl._types import Iir
 from pyGHDL.libghdl.vhdl import nodes
+from pyGHDL.dom import DOMMixin, DOMException
 from pyGHDL.dom._Utils import GetIirKindOfNode
 from pyGHDL.dom.Symbol import SimpleSubtypeSymbol
 from pyGHDL.dom.Aggregates import (
diff --git a/pyGHDL/dom/InterfaceItem.py b/pyGHDL/dom/InterfaceItem.py
index 4ebea735a..9f4d1c5e2 100644
--- a/pyGHDL/dom/InterfaceItem.py
+++ b/pyGHDL/dom/InterfaceItem.py
@@ -32,7 +32,7 @@
 # ============================================================================
 from pydecor import export
 
-from pyVHDLModel.VHDLModel import (
+from pyVHDLModel.SyntaxModel import (
     GenericConstantInterfaceItem as VHDLModel_GenericConstantInterfaceItem,
     GenericTypeInterfaceItem as VHDLModel_GenericTypeInterfaceItem,
     GenericPackageInterfaceItem as VHDLModel_GenericPackageInterfaceItem,
diff --git a/pyGHDL/dom/Literal.py b/pyGHDL/dom/Literal.py
index 784039d45..435563793 100644
--- a/pyGHDL/dom/Literal.py
+++ b/pyGHDL/dom/Literal.py
@@ -9,7 +9,7 @@
 # Authors:
 #   Patrick Lehmann
 #
-# Package module:   DOM: Interface items (e.g. generic or port)
+# Package module:   DOM: Literals.
 #
 # License:
 # ============================================================================
@@ -32,7 +32,7 @@
 # ============================================================================
 from pydecor import export
 
-from pyVHDLModel.VHDLModel import (
+from pyVHDLModel.SyntaxModel import (
     NullLiteral as VHDLModel_NullLiteral,
     EnumerationLiteral as VHDLModel_EnumerationLiteral,
     IntegerLiteral as VHDLModel_IntegerLiteral,
diff --git a/pyGHDL/dom/Misc.py b/pyGHDL/dom/Misc.py
index b80c64a82..ddd31040a 100644
--- a/pyGHDL/dom/Misc.py
+++ b/pyGHDL/dom/Misc.py
@@ -37,12 +37,12 @@
 """
 from pydecor import export
 
-from pyVHDLModel.VHDLModel import (
+from pyVHDLModel.SyntaxModel import (
     Alias as VHDLModel_Alias,
 )
 from pyGHDL.libghdl._types import Iir
-from pyGHDL.dom._Utils import GetNameOfNode
 from pyGHDL.dom import DOMMixin
+from pyGHDL.dom._Utils import GetNameOfNode
 
 
 __all__ = []
diff --git a/pyGHDL/dom/Names.py b/pyGHDL/dom/Names.py
index e09294d40..f98555681 100644
--- a/pyGHDL/dom/Names.py
+++ b/pyGHDL/dom/Names.py
@@ -32,10 +32,9 @@
 # ============================================================================
 from typing import List
 
-from pyGHDL.libghdl._types import Iir
 from pydecor import export
 
-from pyVHDLModel.VHDLModel import (
+from pyVHDLModel.SyntaxModel import (
     SimpleName as VHDLModel_SimpleName,
     ParenthesisName as VHDLModel_ParenthesisName,
     IndexedName as VHDLModel_IndexedName,
@@ -45,6 +44,7 @@ from pyVHDLModel.VHDLModel import (
     AllName as VHDLModel_AllName,
     Name,
 )
+from pyGHDL.libghdl._types import Iir
 from pyGHDL.dom import DOMMixin
 
 __all__ = []
diff --git a/pyGHDL/dom/NonStandard.py b/pyGHDL/dom/NonStandard.py
index bf48db900..41f58732f 100644
--- a/pyGHDL/dom/NonStandard.py
+++ b/pyGHDL/dom/NonStandard.py
@@ -42,8 +42,7 @@ from typing import Any
 
 from pydecor import export
 
-from pyGHDL.dom.PSL import VerificationUnit, VerificationProperty, VerificationMode
-from pyVHDLModel.VHDLModel import (
+from pyVHDLModel.SyntaxModel import (
     Design as VHDLModel_Design,
     Library as VHDLModel_Library,
     Document as VHDLModel_Document,
@@ -73,6 +72,7 @@ from pyGHDL.dom.DesignUnit import (
     Configuration,
     PackageInstantiation,
 )
+from pyGHDL.dom.PSL import VerificationUnit, VerificationProperty, VerificationMode
 
 __all__ = []
 
diff --git a/pyGHDL/dom/Object.py b/pyGHDL/dom/Object.py
index d25acb587..623917661 100644
--- a/pyGHDL/dom/Object.py
+++ b/pyGHDL/dom/Object.py
@@ -32,10 +32,9 @@
 # ============================================================================
 from typing import Union
 
-from pyGHDL.libghdl._types import Iir
 from pydecor import export
 
-from pyVHDLModel.VHDLModel import (
+from pyVHDLModel.SyntaxModel import (
     Constant as VHDLModel_Constant,
     DeferredConstant as VHDLModel_DeferredConstant,
     Variable as VHDLModel_Variable,
@@ -46,6 +45,7 @@ from pyVHDLModel.VHDLModel import (
     SubtypeOrSymbol,
 )
 
+from pyGHDL.libghdl._types import Iir
 from pyGHDL.libghdl.vhdl import nodes
 from pyGHDL.dom import DOMMixin
 from pyGHDL.dom._Utils import GetNameOfNode
diff --git a/pyGHDL/dom/PSL.py b/pyGHDL/dom/PSL.py
index 6c4ba76b3..95ac72082 100644
--- a/pyGHDL/dom/PSL.py
+++ b/pyGHDL/dom/PSL.py
@@ -39,7 +39,6 @@ This module contains all DOM classes for VHDL's design units (:class:`context <E
 
 
 """
-from pyGHDL.libghdl.vhdl import nodes
 from pydecor import export
 
 from pyVHDLModel.PSLModel import (
diff --git a/pyGHDL/dom/Range.py b/pyGHDL/dom/Range.py
index ce8dfbc40..f5153e67d 100644
--- a/pyGHDL/dom/Range.py
+++ b/pyGHDL/dom/Range.py
@@ -32,12 +32,7 @@
 # ============================================================================
 from pydecor import export
 
-from pyVHDLModel.VHDLModel import (
-    Range as VHDLModel_Range,
-    RangeExpression as VHDLModel_RangeExpression,
-    Direction,
-    Expression,
-)
+from pyVHDLModel.SyntaxModel import Range as VHDLModel_Range
 
 __all__ = []
 
diff --git a/pyGHDL/dom/Subprogram.py b/pyGHDL/dom/Subprogram.py
index e8e5ebbb4..32635f693 100644
--- a/pyGHDL/dom/Subprogram.py
+++ b/pyGHDL/dom/Subprogram.py
@@ -34,7 +34,7 @@ from typing import List
 
 from pydecor import export
 
-from pyVHDLModel.VHDLModel import (
+from pyVHDLModel.SyntaxModel import (
     Function as VHDLModel_Function,
     Procedure as VHDLModel_Procedure,
     SubtypeOrSymbol,
diff --git a/pyGHDL/dom/Symbol.py b/pyGHDL/dom/Symbol.py
index 3597f2572..931fc82f2 100644
--- a/pyGHDL/dom/Symbol.py
+++ b/pyGHDL/dom/Symbol.py
@@ -34,7 +34,7 @@ from typing import List, Iterator
 
 from pydecor import export
 
-from pyVHDLModel.VHDLModel import (
+from pyVHDLModel.SyntaxModel import (
     EntitySymbol as VHDLModel_EntitySymbol,
     SimpleSubtypeSymbol as VHDLModel_SimpleSubtypeSymbol,
     ConstrainedScalarSubtypeSymbol as VHDLModel_ConstrainedScalarSubtypeSymbol,
diff --git a/pyGHDL/dom/Type.py b/pyGHDL/dom/Type.py
index efe32afc2..64039c147 100644
--- a/pyGHDL/dom/Type.py
+++ b/pyGHDL/dom/Type.py
@@ -34,7 +34,7 @@ from typing import List, Union, Iterator, Tuple
 
 from pydecor import export
 
-from pyVHDLModel.VHDLModel import (
+from pyVHDLModel.SyntaxModel import (
     AnonymousType as VHDLModel_AnonymousType,
     PhysicalType as VHDLModel_PhysicalType,
     IntegerType as VHDLModel_IntegerType,
diff --git a/pyGHDL/dom/_Translate.py b/pyGHDL/dom/_Translate.py
index fc804caf4..46cb352c7 100644
--- a/pyGHDL/dom/_Translate.py
+++ b/pyGHDL/dom/_Translate.py
@@ -9,7 +9,7 @@
 # Authors:
 #   Patrick Lehmann
 #
-# Package module:   DOM: Interface items (e.g. generic or port)
+# Package module:   DOM: IIR to *** translations.
 #
 # License:
 # ============================================================================
@@ -34,10 +34,7 @@ from typing import List, Generator
 
 from pydecor import export
 
-from pyGHDL.dom import Position, DOMException
-from pyGHDL.dom.Object import Variable
-from pyGHDL.dom.PSL import DefaultClock
-from pyVHDLModel.VHDLModel import (
+from pyVHDLModel.SyntaxModel import (
     Constraint,
     Direction,
     Expression,
@@ -53,6 +50,7 @@ from pyVHDLModel.VHDLModel import (
 from pyGHDL.libghdl import utils
 from pyGHDL.libghdl._types import Iir
 from pyGHDL.libghdl.vhdl import nodes
+from pyGHDL.dom import Position, DOMException
 from pyGHDL.dom._Utils import (
     GetNameOfNode,
     GetIirKindOfNode,
@@ -94,6 +92,7 @@ from pyGHDL.dom.Literal import (
     PhysicalFloatingLiteral,
     NullLiteral,
 )
+from pyGHDL.dom.Object import Variable
 from pyGHDL.dom.Expression import (
     SubtractionExpression,
     AdditionExpression,
@@ -140,6 +139,7 @@ from pyGHDL.dom.Expression import (
 )
 from pyGHDL.dom.Subprogram import Function, Procedure
 from pyGHDL.dom.Misc import Alias
+from pyGHDL.dom.PSL import DefaultClock
 
 
 __all__ = []
diff --git a/pyGHDL/dom/_Utils.py b/pyGHDL/dom/_Utils.py
index 2b17d98ab..dbb39f43d 100644
--- a/pyGHDL/dom/_Utils.py
+++ b/pyGHDL/dom/_Utils.py
@@ -9,7 +9,7 @@
 # Authors:
 #   Patrick Lehmann
 #
-# Package module:   DOM: Interface items (e.g. generic or port)
+# Package module:   DOM: IIR helper functions
 #
 # License:
 # ============================================================================
@@ -32,12 +32,12 @@
 # ============================================================================
 from pydecor import export
 
-from pyVHDLModel.VHDLModel import Mode
+from pyVHDLModel.SyntaxModel import Mode
 
-from pyGHDL.libghdl import LibGHDLException, name_table, files_map, errorout_memory
+from pyGHDL.libghdl import LibGHDLException, name_table, errorout_memory
+from pyGHDL.libghdl._types import Iir
 from pyGHDL.libghdl.vhdl import nodes
 from pyGHDL.libghdl.vhdl.nodes import Null_Iir
-from pyGHDL.libghdl._types import Iir
 from pyGHDL.dom import DOMException
 
 __all__ = []
diff --git a/pyGHDL/dom/formatting/__init__.py b/pyGHDL/dom/formatting/__init__.py
index e69de29bb..828756001 100644
--- a/pyGHDL/dom/formatting/__init__.py
+++ b/pyGHDL/dom/formatting/__init__.py
@@ -0,0 +1,32 @@
+# =============================================================================
+#               ____ _   _ ____  _          _
+#  _ __  _   _ / ___| | | |  _ \| |      __| | ___  _ __ ___
+# | '_ \| | | | |  _| |_| | | | | |     / _` |/ _ \| '_ ` _ \
+# | |_) | |_| | |_| |  _  | |_| | |___ | (_| | (_) | | | | | |
+# | .__/ \__, |\____|_| |_|____/|_____(_)__,_|\___/|_| |_| |_|
+# |_|    |___/
+# =============================================================================
+# Authors:
+#   Patrick Lehmann
+#
+# Package package:  A package for formatters.
+#
+# License:
+# ============================================================================
+#  Copyright (C) 2019-2021 Tristan Gingold
+#
+#  This program is free software: you can redistribute it and/or modify
+#  it under the terms of the GNU General Public License as published by
+#  the Free Software Foundation, either version 2 of the License, or
+#  (at your option) any later version.
+#
+#  This program is distributed in the hope that it will be useful,
+#  but WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+#  GNU General Public License for more details.
+#
+#  You should have received a copy of the GNU General Public License
+#  along with this program.  If not, see <gnu.org/licenses>.
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+# ============================================================================
diff --git a/pyGHDL/dom/formatting/prettyprint.py b/pyGHDL/dom/formatting/prettyprint.py
index 4d6e5dccb..949935b3f 100644
--- a/pyGHDL/dom/formatting/prettyprint.py
+++ b/pyGHDL/dom/formatting/prettyprint.py
@@ -1,25 +1,40 @@
+# =============================================================================
+#               ____ _   _ ____  _          _
+#  _ __  _   _ / ___| | | |  _ \| |      __| | ___  _ __ ___
+# | '_ \| | | | |  _| |_| | | | | |     / _` |/ _ \| '_ ` _ \
+# | |_) | |_| | |_| |  _  | |_| | |___ | (_| | (_) | | | | | |
+# | .__/ \__, |\____|_| |_|____/|_____(_)__,_|\___/|_| |_| |_|
+# |_|    |___/
+# =============================================================================
+# Authors:
+#   Patrick Lehmann
+#
+# Package module:   A pretty printer to format the DOM as a tree in text form.
+#
+# License:
+# ============================================================================
+#  Copyright (C) 2019-2021 Tristan Gingold
+#
+#  This program is free software: you can redistribute it and/or modify
+#  it under the terms of the GNU General Public License as published by
+#  the Free Software Foundation, either version 2 of the License, or
+#  (at your option) any later version.
+#
+#  This program is distributed in the hope that it will be useful,
+#  but WITHOUT ANY WARRANTY; without even the implied warranty of
+#  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+#  GNU General Public License for more details.
+#
+#  You should have received a copy of the GNU General Public License
+#  along with this program.  If not, see <gnu.org/licenses>.
+#
+# SPDX-License-Identifier: GPL-2.0-or-later
+# ============================================================================
 from typing import List, Union
 
 from pydecor import export
 
-from pyGHDL.dom.Attribute import Attribute, AttributeSpecification
-from pyGHDL.dom.Misc import Alias
-from pyGHDL.dom.PSL import DefaultClock
-from pyGHDL.dom.Subprogram import Procedure
-from pyGHDL.dom.Type import (
-    IntegerType,
-    Subtype,
-    ArrayType,
-    RecordType,
-    AccessType,
-    EnumeratedType,
-    FileType,
-    ProtectedType,
-    ProtectedTypeBody,
-    PhysicalType,
-    IncompleteType,
-)
-from pyVHDLModel.VHDLModel import (
+from pyVHDLModel.SyntaxModel import (
     GenericInterfaceItem,
     NamedEntity,
     PortInterfaceItem,
@@ -42,16 +57,33 @@ from pyGHDL.dom.DesignUnit import (
     UseClause,
     PackageInstantiation,
 )
-from pyGHDL.dom.Object import Constant, Signal, SharedVariable, File
+from pyGHDL.dom.Symbol import (
+    SimpleSubtypeSymbol,
+    ConstrainedCompositeSubtypeSymbol,
+)
+from pyGHDL.dom.Type import (
+    IntegerType,
+    Subtype,
+    ArrayType,
+    RecordType,
+    AccessType,
+    EnumeratedType,
+    FileType,
+    ProtectedType,
+    ProtectedTypeBody,
+    PhysicalType,
+    IncompleteType,
+)
 from pyGHDL.dom.InterfaceItem import (
     GenericConstantInterfaceItem,
     PortSignalInterfaceItem,
     GenericTypeInterfaceItem,
 )
-from pyGHDL.dom.Symbol import (
-    SimpleSubtypeSymbol,
-    ConstrainedCompositeSubtypeSymbol,
-)
+from pyGHDL.dom.Object import Constant, Signal, SharedVariable, File
+from pyGHDL.dom.Attribute import Attribute, AttributeSpecification
+from pyGHDL.dom.Subprogram import Procedure
+from pyGHDL.dom.Misc import Alias
+from pyGHDL.dom.PSL import DefaultClock
 
 
 StringBuffer = List[str]
diff --git a/pyGHDL/dom/requirements.txt b/pyGHDL/dom/requirements.txt
index 66e3025ae..ca2a796ac 100644
--- a/pyGHDL/dom/requirements.txt
+++ b/pyGHDL/dom/requirements.txt
@@ -1,4 +1,4 @@
 -r ../libghdl/requirements.txt
 
-pyVHDLModel==0.11.1
-#https://github.com/VHDL/pyVHDLModel/archive/dev.zip#pyVHDLModel
+#pyVHDLModel==0.11.2
+https://github.com/VHDL/pyVHDLModel/archive/dev.zip#pyVHDLModel