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authorTristan Gingold <tgingold@free.fr>2023-04-19 20:54:41 +0200
committerTristan Gingold <tgingold@free.fr>2023-04-19 20:55:58 +0200
commitf721c20920414f86d97e025aea8587e116368471 (patch)
treedb95483817541435c41257581095f4b83c6062a7
parente14a831260a11f241bb4cf393e75faae21308bbe (diff)
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testsuite/synth: add a test for #2418
-rw-r--r--testsuite/synth/issue2418/ent.vhdl21
-rwxr-xr-xtestsuite/synth/issue2418/testsuite.sh7
2 files changed, 28 insertions, 0 deletions
diff --git a/testsuite/synth/issue2418/ent.vhdl b/testsuite/synth/issue2418/ent.vhdl
new file mode 100644
index 000000000..b3ffd064a
--- /dev/null
+++ b/testsuite/synth/issue2418/ent.vhdl
@@ -0,0 +1,21 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity ent is
+ port (
+ sel : in std_logic_vector(1 downto 0)
+ );
+end entity ent;
+
+architecture arch of ent is
+ signal reg : std_logic_vector(7 downto 0);
+begin
+ process(sel)
+ begin
+ reg <= (others => '0');
+
+ -- This is the line that causes the error
+ reg(to_integer(unsigned(sel)) + 1 downto to_integer(unsigned(sel))) <= (others => '1');
+ end process;
+end architecture arch;
diff --git a/testsuite/synth/issue2418/testsuite.sh b/testsuite/synth/issue2418/testsuite.sh
new file mode 100755
index 000000000..08ebf93a4
--- /dev/null
+++ b/testsuite/synth/issue2418/testsuite.sh
@@ -0,0 +1,7 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+synth_only ent
+
+echo "Test successful"