synth: add test for previous commit.

3 files changed, 49 insertions, 1 deletions

diff --git a/testsuite/synth/insert01/insert02.vhdl b/testsuite/synth/insert01/insert02.vhdl
new file mode 100644
index 000000000..5f7b7e6c3
--- /dev/null
+++ b/testsuite/synth/insert01/insert02.vhdl
@@ -0,0 +1,23 @@
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity insert02 is
+  port (a : std_logic_vector (3 downto 0);
+        b : std_logic_vector (1 downto 0);
+        o0, o1, o2 : out std_logic_vector (3 downto 0));
+end insert02;
+
+architecture behav of insert02 is
+begin
+  process(a, b)
+  begin
+    o0 <= a;
+    o0 (1 downto 0) <= b;
+
+    o1 <= a;
+    o1 (2 downto 1) <= b;
+    
+    o2 <= a;
+    o2 (3 downto 2) <= b;
+  end process;
+end behav;
diff --git a/testsuite/synth/insert01/tb_insert02.vhdl b/testsuite/synth/insert01/tb_insert02.vhdl
new file mode 100644
index 000000000..b2b125288
--- /dev/null
+++ b/testsuite/synth/insert01/tb_insert02.vhdl
@@ -0,0 +1,25 @@
+entity tb_insert02 is
+end tb_insert02;
+
+library ieee;
+use ieee.std_logic_1164.all;
+
+architecture behav of tb_insert02 is
+  signal a : std_logic_vector (3 downto 0);
+  signal b : std_logic_vector (1 downto 0);
+  signal o0, o1, o2 : std_logic_vector (3 downto 0);
+begin
+  dut: entity work.insert02
+    port map (a, b, o0, o1, o2);
+
+  process
+  begin
+    a <= "0111";
+    b <= "10";
+    wait for 1 ns;
+    assert o0 = "0110" severity failure;
+    assert o1 = "0101" severity failure;
+    assert o2 = "1011" severity failure;
+    wait;
+  end process;
+end behav;
diff --git a/testsuite/synth/insert01/testsuite.sh b/testsuite/synth/insert01/testsuite.sh
index a3ebaaa0d..861ec8b04 100755
--- a/testsuite/synth/insert01/testsuite.sh
+++ b/testsuite/synth/insert01/testsuite.sh
@@ -2,7 +2,7 @@
 
 . ../../testenv.sh
 
-for t in insert01; do
+for t in insert01 insert02; do
     analyze $t.vhdl tb_$t.vhdl
     elab_simulate tb_$t
     clean