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-rw-r--r--testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/above_attr.ams4
1 files changed, 2 insertions, 2 deletions
diff --git a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/above_attr.ams b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/above_attr.ams
index c3bf7abd0..1d3f0c689 100644
--- a/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/above_attr.ams
+++ b/testsuite/vests/vhdl-ams/ad-hoc/fromUC/interface_models/above_attr.ams
@@ -65,7 +65,7 @@ ABSIG<=V1'above(V2+1.0);
testbench:PROCESS
VARIABLE outline : LINE;
- VARIABLE Headline : string(1 TO 33) :=
+ VARIABLE Headline : string(1 TO 10) :=
"time ABSIG";
VARIABLE seperator : string(1 TO 1) := " ";
VARIABLE flag : bit := '0';
@@ -77,7 +77,7 @@ ABSIG<=V1'above(V2+1.0);
WRITE(outline,Headline);
WRITELINE(outfile,outline);
ELSE
- WRITE(outline, now);
+ WRITE(outline, time'(now));
WRITE(outline,seperator);
IF (ABSIG = true) THEN
tmp:='1';