vhdl: minor refactoring

4 files changed, 13 insertions, 22 deletions

diff --git a/src/vhdl/vhdl-sem.adb b/src/vhdl/vhdl-sem.adb
index 220a223bb..528b642a1 100644
--- a/src/vhdl/vhdl-sem.adb
+++ b/src/vhdl/vhdl-sem.adb
@@ -622,7 +622,7 @@ package body Vhdl.Sem is
             --  FIXME: it is possible to have port unassociated ?
             Miss := Missing_Port;
          when others =>
-            Error_Kind ("sem_port_association_list", Assoc_Parent);
+            Error_Kind ("sem_port_association_chain", Assoc_Parent);
       end case;
 
       --  The ports
@@ -690,18 +690,6 @@ package body Vhdl.Sem is
       end loop;
    end Sem_Port_Association_Chain;
 
-   --  INTER_PARENT contains generics and ports interfaces;
-   --  ASSOC_PARENT constains generics and ports map aspects.
-   procedure Sem_Generic_Port_Association_Chain
-     (Inter_Parent : Iir; Assoc_Parent : Iir)
-   is
-      Res : Boolean;
-      pragma Unreferenced (Res);
-   begin
-      Sem_Generic_Association_Chain (Inter_Parent, Assoc_Parent);
-      Sem_Port_Association_Chain (Inter_Parent, Assoc_Parent);
-   end Sem_Generic_Port_Association_Chain;
-
    --  LRM 1.3  Configuration Declarations.
    procedure Sem_Configuration_Declaration (Decl: Iir)
    is
diff --git a/src/vhdl/vhdl-sem.ads b/src/vhdl/vhdl-sem.ads
index 0e9664563..78fd1fac1 100644
--- a/src/vhdl/vhdl-sem.ads
+++ b/src/vhdl/vhdl-sem.ads
@@ -34,16 +34,16 @@ package Vhdl.Sem is
    --  Add EL in the current design unit list of items to be checked later.
    procedure Add_Analysis_Checks_List (El : Iir);
 
-   --  INTER_PARENT contains generics and ports interfaces;
-   --  ASSOC_PARENT constains generics and ports map aspects.
-   procedure Sem_Generic_Port_Association_Chain
-     (Inter_Parent : Iir; Assoc_Parent : Iir);
-
    --  INTER_PARENT contains generics interfaces;
    --  ASSOC_PARENT constains generic aspects.
    procedure Sem_Generic_Association_Chain
      (Inter_Parent : Iir; Assoc_Parent : Iir);
 
+   --  INTER_PARENT contains ports interfaces;
+   --  ASSOC_PARENT constains ports map aspects.
+   procedure Sem_Port_Association_Chain
+     (Inter_Parent : Iir; Assoc_Parent : Iir);
+
    --  Return TRUE iff the actual of ASSOC can be the formal FORMAL.
    --  ASSOC must be an association_element_by_expression.
    function Can_Collapse_Signals (Assoc : Iir; Formal : Iir) return Boolean;
diff --git a/src/vhdl/vhdl-sem_specs.adb b/src/vhdl/vhdl-sem_specs.adb
index dff9e6da2..dbc3e376c 100644
--- a/src/vhdl/vhdl-sem_specs.adb
+++ b/src/vhdl/vhdl-sem_specs.adb
@@ -1477,7 +1477,8 @@ package body Vhdl.Sem_Specs is
             return;
          end if;
       else
-         Sem_Generic_Port_Association_Chain (Entity, Bind);
+         Sem_Generic_Association_Chain (Entity, Bind);
+         Sem_Port_Association_Chain (Entity, Bind);
 
          --  If the binding is final (cannot be incrementally bound), check
          --  that all generics are associated when required (like no default
diff --git a/src/vhdl/vhdl-sem_stmts.adb b/src/vhdl/vhdl-sem_stmts.adb
index ad0a4bccc..74409ccab 100644
--- a/src/vhdl/vhdl-sem_stmts.adb
+++ b/src/vhdl/vhdl-sem_stmts.adb
@@ -1970,8 +1970,9 @@ package body Vhdl.Sem_Stmts is
          return;
       end if;
 
-      --  The association
-      Sem_Generic_Port_Association_Chain (Decl, Stmt);
+      --  The associations
+      Sem_Generic_Association_Chain (Decl, Stmt);
+      Sem_Port_Association_Chain (Decl, Stmt);
 
       --  FIXME: add sources for signals, in order to detect multiple sources
       --  to unresolved signals.
@@ -2094,7 +2095,8 @@ package body Vhdl.Sem_Stmts is
          Set_Is_Within_Flag (Stmt, False);
          Close_Declarative_Region;
 
-         Sem_Generic_Port_Association_Chain (Header, Header);
+         Sem_Generic_Association_Chain (Header, Header);
+         Sem_Port_Association_Chain (Header, Header);
 
          --  ... and reopen-it.
          Open_Declarative_Region;