1 files changed, 5 insertions, 5 deletions
diff --git a/src/vhdl/vhdl-sem.ads b/src/vhdl/vhdl-sem.ads
index 0e9664563..78fd1fac1 100644
--- a/src/vhdl/vhdl-sem.ads
+++ b/src/vhdl/vhdl-sem.ads
@@ -34,16 +34,16 @@ package Vhdl.Sem is
    --  Add EL in the current design unit list of items to be checked later.
    procedure Add_Analysis_Checks_List (El : Iir);
 
-   --  INTER_PARENT contains generics and ports interfaces;
-   --  ASSOC_PARENT constains generics and ports map aspects.
-   procedure Sem_Generic_Port_Association_Chain
-     (Inter_Parent : Iir; Assoc_Parent : Iir);
-
    --  INTER_PARENT contains generics interfaces;
    --  ASSOC_PARENT constains generic aspects.
    procedure Sem_Generic_Association_Chain
      (Inter_Parent : Iir; Assoc_Parent : Iir);
 
+   --  INTER_PARENT contains ports interfaces;
+   --  ASSOC_PARENT constains ports map aspects.
+   procedure Sem_Port_Association_Chain
+     (Inter_Parent : Iir; Assoc_Parent : Iir);
+
    --  Return TRUE iff the actual of ASSOC can be the formal FORMAL.
    --  ASSOC must be an association_element_by_expression.
    function Can_Collapse_Signals (Assoc : Iir; Formal : Iir) return Boolean;