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author | Tristan Gingold <tgingold@free.fr> | 2019-10-07 07:21:05 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-10-07 07:21:05 +0200 |
commit | ab9bb439cc6a108b3fae713c3e475aac2ca509a0 (patch) | |
tree | 8cfae3097a458f8a9064adbe3c9d30f43fbe53ee | |
parent | 873285ee12f887f11d14a140c7a420ce4c54a9bb (diff) | |
download | ghdl-ab9bb439cc6a108b3fae713c3e475aac2ca509a0.tar.gz ghdl-ab9bb439cc6a108b3fae713c3e475aac2ca509a0.tar.bz2 ghdl-ab9bb439cc6a108b3fae713c3e475aac2ca509a0.zip |
testsuite/synth: add testcase for #972
-rw-r--r-- | testsuite/synth/issue972/test2.vhdl | 18 | ||||
-rwxr-xr-x | testsuite/synth/issue972/testsuite.sh | 11 |
2 files changed, 29 insertions, 0 deletions
diff --git a/testsuite/synth/issue972/test2.vhdl b/testsuite/synth/issue972/test2.vhdl new file mode 100644 index 000000000..11192fafd --- /dev/null +++ b/testsuite/synth/issue972/test2.vhdl @@ -0,0 +1,18 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +entity test2 is + port( + d_in: in std_ulogic_vector(63 downto 0); + d_out: out std_ulogic_vector(63 downto 0) + ); +end entity test2; + +architecture behaviour of test2 is +begin + comb : process(all) + begin + d_out <= std_logic_vector(unsigned(d_in) + 4); + end process; +end architecture behaviour; diff --git a/testsuite/synth/issue972/testsuite.sh b/testsuite/synth/issue972/testsuite.sh new file mode 100755 index 000000000..c3844e039 --- /dev/null +++ b/testsuite/synth/issue972/testsuite.sh @@ -0,0 +1,11 @@ +#! /bin/sh + +. ../../testenv.sh + +GHDL_STD_FLAGS=--std=08 + +analyze test2.vhdl +synth test2 > syn_test2.vhdl +clean + +echo "Test successful" |