From ab9bb439cc6a108b3fae713c3e475aac2ca509a0 Mon Sep 17 00:00:00 2001
From: Tristan Gingold <tgingold@free.fr>
Date: Mon, 7 Oct 2019 07:21:05 +0200
Subject: testsuite/synth: add testcase for #972

---
 testsuite/synth/issue972/test2.vhdl   | 18 ++++++++++++++++++
 testsuite/synth/issue972/testsuite.sh | 11 +++++++++++
 2 files changed, 29 insertions(+)
 create mode 100644 testsuite/synth/issue972/test2.vhdl
 create mode 100755 testsuite/synth/issue972/testsuite.sh

diff --git a/testsuite/synth/issue972/test2.vhdl b/testsuite/synth/issue972/test2.vhdl
new file mode 100644
index 000000000..11192fafd
--- /dev/null
+++ b/testsuite/synth/issue972/test2.vhdl
@@ -0,0 +1,18 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity test2 is
+    port(
+        d_in: in std_ulogic_vector(63 downto 0);
+        d_out: out std_ulogic_vector(63 downto 0)
+        );
+end entity test2;
+
+architecture behaviour of test2 is
+begin
+    comb : process(all)
+    begin
+        d_out <= std_logic_vector(unsigned(d_in) + 4);
+    end process;
+end architecture behaviour;
diff --git a/testsuite/synth/issue972/testsuite.sh b/testsuite/synth/issue972/testsuite.sh
new file mode 100755
index 000000000..c3844e039
--- /dev/null
+++ b/testsuite/synth/issue972/testsuite.sh
@@ -0,0 +1,11 @@
+#! /bin/sh
+
+. ../../testenv.sh
+
+GHDL_STD_FLAGS=--std=08
+
+analyze test2.vhdl
+synth test2 > syn_test2.vhdl
+clean
+
+echo "Test successful"
-- 
cgit v1.2.3