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| author | Tristan Gingold <tgingold@free.fr> | 2019-07-02 19:02:04 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-07-02 19:02:04 +0200 |
| commit | 82e5fc7bf210aa3339ac347e921f4b941af7d827 (patch) | |
| tree | 5af78eb83da413dbed8ec841487f1a98728915d8 | |
| parent | 818b00f30376d766c6d6cfcfc41a7dcc388a2cb9 (diff) | |
| download | ghdl-82e5fc7bf210aa3339ac347e921f4b941af7d827.tar.gz ghdl-82e5fc7bf210aa3339ac347e921f4b941af7d827.tar.bz2 ghdl-82e5fc7bf210aa3339ac347e921f4b941af7d827.zip | |
netlists-disp_vhdl: handle xor.
| -rw-r--r-- | src/synth/netlists-disp_vhdl.adb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb index 0b86f1b9c..bf53b4d1d 100644 --- a/src/synth/netlists-disp_vhdl.adb +++ b/src/synth/netlists-disp_vhdl.adb @@ -578,6 +578,8 @@ package body Netlists.Disp_Vhdl is Disp_Template (" \o0 <= \i0 or \i1;" & NL, Inst); when Id_And => Disp_Template (" \o0 <= \i0 and \i1;" & NL, Inst); + when Id_Xor => + Disp_Template (" \o0 <= \i0 xor \i1;" & NL, Inst); when Id_Concat2 => Disp_Template (" \o0 <= \i0 & \i1;" & NL, Inst); when Id_Concat3 => |