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| author | Tristan Gingold <tgingold@free.fr> | 2019-07-02 19:01:57 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-07-02 19:01:57 +0200 |
| commit | 818b00f30376d766c6d6cfcfc41a7dcc388a2cb9 (patch) | |
| tree | 13ddeac5a786eb017ee3d51283a87fe048cfd188 | |
| parent | 56f6228c42f05ca9079b0c62a32a45bf7d46f9c9 (diff) | |
| download | ghdl-818b00f30376d766c6d6cfcfc41a7dcc388a2cb9.tar.gz ghdl-818b00f30376d766c6d6cfcfc41a7dcc388a2cb9.tar.bz2 ghdl-818b00f30376d766c6d6cfcfc41a7dcc388a2cb9.zip | |
synth: fix Idff; fix 'edge and enable'.
| -rw-r--r-- | src/synth/netlists-builders.adb | 2 | ||||
| -rw-r--r-- | src/synth/synth-inference.adb | 13 |
2 files changed, 6 insertions, 9 deletions
diff --git a/src/synth/netlists-builders.adb b/src/synth/netlists-builders.adb index 957ba565c..f52ac4f56 100644 --- a/src/synth/netlists-builders.adb +++ b/src/synth/netlists-builders.adb @@ -397,7 +397,7 @@ package body Netlists.Builders is Create_Monadic_Module (Design, Res.M_Extend (Id_Sextend), Get_Identifier ("sextend"), Id_Sextend); - Create_Edge_Module (Res, Res.M_Edge, Name_Posedge); + Create_Edge_Module (Res, Res.M_Edge, Name_Edge); Create_Mux_Modules (Res); Create_Objects_Module (Res); diff --git a/src/synth/synth-inference.adb b/src/synth/synth-inference.adb index cb7a0ee41..6e0ba1648 100644 --- a/src/synth/synth-inference.adb +++ b/src/synth/synth-inference.adb @@ -160,19 +160,16 @@ package body Synth.Inference is -- CLK and EXPR. -- FIXME: do it! declare - I0 : constant Input := Get_Input (Inst, 0); - I1 : Input; - Drv : Net; + I0 : constant Net := Get_Input_Net (Inst, 0); + Inst0 : constant Instance := Get_Net_Parent (I0); begin - Drv := Get_Driver (I0); - if Get_Id (Get_Net_Parent (Drv)) = Id_Edge then + if Get_Id (Inst0) = Id_Edge then -- INST is clearly not synthesizable (boolean operation on -- an edge). Will be removed at the end by -- remove_unused_instances. Do not remove it now as its -- output may be used by other nets. - Clk := Drv; - I1 := Get_Input (Inst, 1); - Enable := Get_Driver (I1); + Clk := Get_Input_Net (Inst0, 0); + Enable := Get_Input_Net (Inst, 1); end if; end; when others => |