Added handling of Floating Point.

4 files changed, 28 insertions, 10 deletions

diff --git a/pyGHDL/dom/InterfaceItem.py b/pyGHDL/dom/InterfaceItem.py
index 028adc690..fcb8b0ef3 100644
--- a/pyGHDL/dom/InterfaceItem.py
+++ b/pyGHDL/dom/InterfaceItem.py
@@ -30,6 +30,9 @@
 #
 # SPDX-License-Identifier: GPL-2.0-or-later
 # ============================================================================
+from pyGHDL.libghdl.vhdl.nodes import Null_Iir
+
+from pyGHDL.libghdl.vhdl import nodes
 from pydecor import export
 
 from pyVHDLModel.VHDLModel import (
@@ -41,7 +44,7 @@ from pyVHDLModel.VHDLModel import (
 )
 
 from pyGHDL.dom._Utils import NodeToName, GetModeOfNode
-from pyGHDL.dom._Translate import GetSubtypeIndicationFromNode
+from pyGHDL.dom._Translate import GetSubtypeIndicationFromNode, GetExpressionFromNode
 from pyGHDL.dom.Common import GHDLMixin
 
 __all__ = []
@@ -54,14 +57,16 @@ class GenericConstantInterfaceItem(VHDLModel_GenericConstantInterfaceItem, GHDLM
         name = NodeToName(generic)
         mode = GetModeOfNode(generic)
         subTypeIndication = GetSubtypeIndicationFromNode(generic, "generic", name)
+        value = GetExpressionFromNode(nodes.Get_Default_Value(generic))
 
-        generic = cls(name, mode, subTypeIndication)
+        generic = cls(name, mode, subTypeIndication, value)
 
         return generic
 
-    def __init__(self, name: str, mode: Mode, subType: SubTypeOrSymbol):
+    def __init__(self, name: str, mode: Mode, subType: SubTypeOrSymbol, defaultExpression: Expression):
         super().__init__(name=name, mode=mode)
         self._subType = subType
+        self._defaultExpression = defaultExpression
 
 
 @export
@@ -72,7 +77,10 @@ class PortSignalInterfaceItem(VHDLModel_PortSignalInterfaceItem, GHDLMixin):
         mode = GetModeOfNode(port)
         subTypeIndication = GetSubtypeIndicationFromNode(port, "port", name)
 
-        port = cls(name, mode, subTypeIndication)
+        defaultValue = nodes.Get_Default_Value(port)
+        value = GetExpressionFromNode(defaultValue) if defaultValue != Null_Iir else None
+
+        port = cls(name, mode, subTypeIndication, value)
 
         return port
 
diff --git a/pyGHDL/dom/Literal.py b/pyGHDL/dom/Literal.py
index 7c722583b..8b32d7163 100644
--- a/pyGHDL/dom/Literal.py
+++ b/pyGHDL/dom/Literal.py
@@ -57,7 +57,7 @@ class FloatingPointLiteral(VHDLModel_FloatingPointLiteral):
     @classmethod
     def parse(cls, node):
         value = nodes.Get_Fp_Value(node)
-        return cls(value)
+        return cls(float(value))
 
 
 @export
diff --git a/pyGHDL/dom/formatting/prettyprint.py b/pyGHDL/dom/formatting/prettyprint.py
index 387706cac..7129a30c4 100644
--- a/pyGHDL/dom/formatting/prettyprint.py
+++ b/pyGHDL/dom/formatting/prettyprint.py
@@ -12,7 +12,7 @@ from pyVHDLModel.VHDLModel import (
     PortInterfaceItem,
     BinaryExpression,
     IdentityExpression,
-    UnaryExpression,
+    UnaryExpression, WithDefaultExpression,
 )
 
 from pyGHDL import GHDLBaseException
@@ -220,16 +220,17 @@ class PrettyPrint:
         subType = generic.SubType
         if isinstance(subType, SimpleSubTypeSymbol):
             buffer.append(
-                "{prefix}  - {name} : {mode} {type}".format(
+                "{prefix}  - {name} : {mode} {type}{initialValue}".format(
                     prefix=prefix,
                     name=generic.Name,
                     mode=ModeTranslation[generic.Mode],
                     type=subType.SymbolName,
+                    initialValue=self.formatInitialValue(generic),
                 )
             )
         elif isinstance(subType, ConstrainedSubTypeSymbol):
             buffer.append(
-                "{prefix}  - {name} : {mode} {type}({constraints})".format(
+                "{prefix}  - {name} : {mode} {type}({constraints}){initialValue}".format(
                     prefix=prefix,
                     name=generic.Name,
                     mode=ModeTranslation[generic.Mode],
@@ -246,6 +247,7 @@ class PrettyPrint:
                             for constraint in subType.Constraints
                         ]
                     ),
+                    initialValue=self.formatInitialValue(generic),
                 )
             )
         else:
@@ -264,13 +266,14 @@ class PrettyPrint:
         prefix = "  " * level
 
         buffer.append(
-            "{prefix}  - {name} : {mode} {subtypeindication}".format(
+            "{prefix}  - {name} : {mode} {subtypeindication}{initialValue}".format(
                 prefix=prefix,
                 name=port.Name,
                 mode=ModeTranslation[port.Mode],
                 subtypeindication=self.formatSubtypeIndication(
                     port.SubType, "port", port.Name
                 ),
+                initialValue=self.formatInitialValue(port),
             )
         )
 
@@ -336,6 +339,12 @@ class PrettyPrint:
                 )
             )
 
+    def formatInitialValue(self, item: WithDefaultExpression) -> str:
+        if item.DefaultExpression is None:
+            return ""
+
+        return " := {expr}".format(expr=self.formatExpression(item.DefaultExpression))
+
     def formatExpression(self, expression: Expression) -> str:
         if isinstance(expression, SimpleObjectSymbol):
             return "{name}".format(name=expression.SymbolName)
diff --git a/testsuite/pyunit/SimpleEntity.vhdl b/testsuite/pyunit/SimpleEntity.vhdl
index 98d0afbb7..9997c8d6d 100644
--- a/testsuite/pyunit/SimpleEntity.vhdl
+++ b/testsuite/pyunit/SimpleEntity.vhdl
@@ -4,11 +4,12 @@ use     ieee.numeric_std.all;
 
 entity entity_1 is
 	generic (
+		FREQ : real     := 100.0;
 		BITS : positive := 8
 	);
 	port (
 	  Clock: in  std_logic;
-	  Reset: in  std_logic;
+	  Reset: in  std_logic := '0';
 	  Q:     out std_logic_vector(BITS - 1 downto 0)
 	);
 end entity entity_1;