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-rw-r--r--testsuite/pyunit/SimpleEntity.vhdl3
1 files changed, 2 insertions, 1 deletions
diff --git a/testsuite/pyunit/SimpleEntity.vhdl b/testsuite/pyunit/SimpleEntity.vhdl
index 98d0afbb7..9997c8d6d 100644
--- a/testsuite/pyunit/SimpleEntity.vhdl
+++ b/testsuite/pyunit/SimpleEntity.vhdl
@@ -4,11 +4,12 @@ use ieee.numeric_std.all;
entity entity_1 is
generic (
+ FREQ : real := 100.0;
BITS : positive := 8
);
port (
Clock: in std_logic;
- Reset: in std_logic;
+ Reset: in std_logic := '0';
Q: out std_logic_vector(BITS - 1 downto 0)
);
end entity entity_1;