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| author | Tristan Gingold <tgingold@free.fr> | 2021-10-18 07:48:03 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2021-10-18 07:55:01 +0200 |
| commit | 7e36182602ff1a2c43723240860029ad8ae007b5 (patch) | |
| tree | b432f0db6d79e1d8c00210a5869e19275f6e999f | |
| parent | fb25becab1caec74a5318ef4ac693f08e1c1f156 (diff) | |
| download | ghdl-7e36182602ff1a2c43723240860029ad8ae007b5.tar.gz ghdl-7e36182602ff1a2c43723240860029ad8ae007b5.tar.bz2 ghdl-7e36182602ff1a2c43723240860029ad8ae007b5.zip | |
synth-static_oper: handle or/and reduce operators for unsigned. Fix #1896
| -rw-r--r-- | src/synth/synth-static_oper.adb | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/src/synth/synth-static_oper.adb b/src/synth/synth-static_oper.adb index 2b9b5ffab..5eba9c8fb 100644 --- a/src/synth/synth-static_oper.adb +++ b/src/synth/synth-static_oper.adb @@ -721,7 +721,11 @@ package body Synth.Static_Oper is (Std_Ulogic'Pos (Not_Table (Read_Std_Logic (Operand.Mem, 0))), Oper_Typ); - when Iir_Predefined_Ieee_1164_Or_Suv => + when Iir_Predefined_Ieee_Numeric_Std_And_Uns => + return Synth_Vector_Reduce ('1', Operand, And_Table); + + when Iir_Predefined_Ieee_1164_Or_Suv + | Iir_Predefined_Ieee_Numeric_Std_Or_Uns => return Synth_Vector_Reduce ('0', Operand, Or_Table); when Iir_Predefined_Ieee_1164_Xor_Suv => return Synth_Vector_Reduce ('0', Operand, Xor_Table); |