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author | Pepijn de Vos <pepijndevos@gmail.com> | 2019-05-28 19:06:48 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-05-28 19:06:48 +0200 |
commit | 7619ac406427a30e2963e11ad67b43b6aae26ee5 (patch) | |
tree | f4e76290176d7ba88a1069f13e723b3254d8a890 | |
parent | ddae75977eac872eecaa7c3f45003f6bb1ecd068 (diff) | |
download | ghdl-7619ac406427a30e2963e11ad67b43b6aae26ee5.tar.gz ghdl-7619ac406427a30e2963e11ad67b43b6aae26ee5.tar.bz2 ghdl-7619ac406427a30e2963e11ad67b43b6aae26ee5.zip |
synth: add support for constants.
Close #815
-rw-r--r-- | src/synth/synth-decls.adb | 2 | ||||
-rw-r--r-- | src/synth/synth-expr.adb | 8 | ||||
-rw-r--r-- | testsuite/synth/dff01/dff09.vhdl | 22 | ||||
-rw-r--r-- | testsuite/synth/dff01/dff10.vhdl | 25 | ||||
-rwxr-xr-x | testsuite/synth/dff01/testsuite.sh | 2 |
5 files changed, 58 insertions, 1 deletions
diff --git a/src/synth/synth-decls.adb b/src/synth/synth-decls.adb index 576a90918..545e3b408 100644 --- a/src/synth/synth-decls.adb +++ b/src/synth/synth-decls.adb @@ -76,6 +76,8 @@ package body Synth.Decls is -- Ignore default value. Make_Object (Syn_Inst, Wire_Variable, Decl); Create_Var_Wire (Syn_Inst, Decl, null); + when Iir_Kind_Constant_Declaration => + null; when Iir_Kind_Signal_Declaration => declare Def : constant Iir := Get_Default_Value (Decl); diff --git a/src/synth/synth-expr.adb b/src/synth/synth-expr.adb index 51e187f4f..147ce8a1b 100644 --- a/src/synth/synth-expr.adb +++ b/src/synth/synth-expr.adb @@ -25,6 +25,7 @@ with Vhdl.Ieee.Std_Logic_1164; with Vhdl.Std_Package; with Vhdl.Errors; use Vhdl.Errors; with Simul.Execution; +with Simul.Annotations; use Simul.Annotations; with Grt.Types; use Grt.Types; with Synth.Errors; use Synth.Errors; @@ -522,6 +523,10 @@ package body Synth.Expr is | Iir_Kind_Variable_Declaration | Iir_Kind_Signal_Declaration => return Get_Value (Syn_Inst, Name); + when Iir_Kind_Constant_Declaration => + return Create_Value_Lit( + Syn_Inst.Sim.Objects(Get_Info(Name).Slot), + Get_Type(Name)); when others => Error_Kind ("synth_name", Name); end case; @@ -840,7 +845,8 @@ package body Synth.Expr is return Synth_Slice_Name (Syn_Inst, Expr); when Iir_Kind_Character_Literal | Iir_Kind_Integer_Literal - | Iir_Kind_String_Literal8 => + | Iir_Kind_String_Literal8 + | Iir_Kind_Enumeration_Literal => return Create_Value_Lit (Simul.Execution.Execute_Expression (Syn_Inst.Sim, Expr), Get_Base_Type (Get_Type (Expr))); diff --git a/testsuite/synth/dff01/dff09.vhdl b/testsuite/synth/dff01/dff09.vhdl new file mode 100644 index 000000000..9dcf4065a --- /dev/null +++ b/testsuite/synth/dff01/dff09.vhdl @@ -0,0 +1,22 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity dff09 is + port (q : out std_logic; + d : std_logic; + clk : std_logic; + rstn : std_logic); +end dff09; + +architecture behav of dff09 is +begin + process (clk, rstn) is + constant rval : std_logic := '0'; + begin + if rstn = '0' then + q <= rval; + elsif rising_edge (clk) then + q <= d; + end if; + end process; +end behav; diff --git a/testsuite/synth/dff01/dff10.vhdl b/testsuite/synth/dff01/dff10.vhdl new file mode 100644 index 000000000..86af44865 --- /dev/null +++ b/testsuite/synth/dff01/dff10.vhdl @@ -0,0 +1,25 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity dff10 is + port (q : out std_logic_vector(7 downto 0); + d : std_logic_vector(7 downto 0); + clk : std_logic; + rst : std_logic; + en : std_logic); +end dff10; + +architecture behav of dff10 is +begin + process (clk) is + constant rval : std_logic_vector(7 downto 0) := x"55"; + begin + if rst = '1' then + q <= rval; + elsif rising_edge (clk) then + if en = '1' then + q <= d; + end if; + end if; + end process; +end behav; diff --git a/testsuite/synth/dff01/testsuite.sh b/testsuite/synth/dff01/testsuite.sh index 216c2dbce..a41248549 100755 --- a/testsuite/synth/dff01/testsuite.sh +++ b/testsuite/synth/dff01/testsuite.sh @@ -10,6 +10,8 @@ synth dff05.vhdl -e dff05 synth dff06.vhdl -e dff06 synth dff07.vhdl -e dff07 synth dff08.vhdl -e dff08 +synth dff09.vhdl -e dff09 +synth dff10.vhdl -e dff10 clean |