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author | Tristan Gingold <tgingold@free.fr> | 2019-05-28 18:54:19 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-05-28 18:54:19 +0200 |
commit | ddae75977eac872eecaa7c3f45003f6bb1ecd068 (patch) | |
tree | c43fa9d4503b1ec0de181cb1984a0a154f8143c8 | |
parent | b2e6d5df3bd55b51214bcc4c8458cab2561b97bf (diff) | |
download | ghdl-ddae75977eac872eecaa7c3f45003f6bb1ecd068.tar.gz ghdl-ddae75977eac872eecaa7c3f45003f6bb1ecd068.tar.bz2 ghdl-ddae75977eac872eecaa7c3f45003f6bb1ecd068.zip |
Add testcase for #828
-rw-r--r-- | testsuite/gna/issue828/test.vhdl | 41 | ||||
-rw-r--r-- | testsuite/gna/issue828/test1.vhdl | 37 | ||||
-rw-r--r-- | testsuite/gna/issue828/test2.vhdl | 36 | ||||
-rwxr-xr-x | testsuite/gna/issue828/testsuite.sh | 14 |
4 files changed, 128 insertions, 0 deletions
diff --git a/testsuite/gna/issue828/test.vhdl b/testsuite/gna/issue828/test.vhdl new file mode 100644 index 000000000..0270ee354 --- /dev/null +++ b/testsuite/gna/issue828/test.vhdl @@ -0,0 +1,41 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity test is + port( + tx : out std_logic); +end entity; + +architecture tb of test is +begin + process + + procedure transmit(data : std_logic_vector; + signal tx : out std_logic) is + + variable norm : std_logic_vector(data'length - 1 downto 0) := data; + + procedure send(value : std_logic) is + begin + tx <= value; + wait for 10 ns; + end procedure; + variable count : natural := 0; + begin + report natural'image (norm'left); + report natural'image (norm'right); + for i in norm'reverse_range loop + send(norm(i)); + report to_string(i); + count := count + 1; + end loop; + assert count = 8 severity failure; + end procedure; + + begin + + transmit(x"55", tx); + wait; + + end process; +end architecture; diff --git a/testsuite/gna/issue828/test1.vhdl b/testsuite/gna/issue828/test1.vhdl new file mode 100644 index 000000000..c55de9363 --- /dev/null +++ b/testsuite/gna/issue828/test1.vhdl @@ -0,0 +1,37 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity test is + port( + tx : out std_logic); +end entity; + +architecture tb of test is +begin + process + + procedure transmit(data : std_logic_vector; + signal tx : out std_logic) is + + variable norm : std_logic_vector(data'length - 1 downto 0) := data; + + procedure send(value : std_logic) is + begin + tx <= value; + wait for 10 ns; + end procedure; + + begin + for i in norm'reverse_range loop + send(norm(i)); + report to_string(i); + end loop; + end procedure; + + begin + + transmit(x"55", tx); + wait; + + end process; +end architecture; diff --git a/testsuite/gna/issue828/test2.vhdl b/testsuite/gna/issue828/test2.vhdl new file mode 100644 index 000000000..298c2fb3c --- /dev/null +++ b/testsuite/gna/issue828/test2.vhdl @@ -0,0 +1,36 @@ +library ieee; +use ieee.std_logic_1164.all; + +entity test2 is + port ( + tx : out std_logic); +end entity; + +architecture tb of test2 is +begin + process + -- variable boolobj: boolean; -- ADDED + procedure transmit(data: std_logic_vector; signal tx: out std_logic) is + variable norm: std_logic_vector(data'length - 1 downto 0) := data; + + procedure send(value: std_logic) is + begin + tx <= value; + wait for 10 ns; + end procedure; + begin + -- report " boolobj = " & boolean'image(boolobj); -- ADDED + for i in norm'reverse_range loop + send(norm(i)); + report integer'image(i); --- to_string(i); -- CHANGED + end loop; + end procedure; + variable norm: std_logic_vector(7 downto 0); -- ADDED + begin + transmit(x"55", tx); + for i in norm'reverse_range loop -- ADDED Loop statement + report "i = " & integer'image(i); + end loop; + wait; + end process; +end architecture; diff --git a/testsuite/gna/issue828/testsuite.sh b/testsuite/gna/issue828/testsuite.sh new file mode 100755 index 000000000..32fa5a0c6 --- /dev/null +++ b/testsuite/gna/issue828/testsuite.sh @@ -0,0 +1,14 @@ +#! /bin/sh + +. ../../testenv.sh + +GHDL_STD_FLAGS=--std=08 +analyze test.vhdl +elab_simulate test + +analyze test2.vhdl +elab_simulate test2 + +clean + +echo "Test successful" |