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| author | Tristan Gingold <tgingold@free.fr> | 2023-04-14 16:47:07 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2023-04-14 16:47:07 +0200 |
| commit | 74faba8044d401ebe3d4ce62c619ee295604ae2d (patch) | |
| tree | f19b7c21ff85b4beb93d13a04b46258ffe0197bc | |
| parent | 6526eae3f265fc490adeeb537eb938b68a4b02d9 (diff) | |
| download | ghdl-74faba8044d401ebe3d4ce62c619ee295604ae2d.tar.gz ghdl-74faba8044d401ebe3d4ce62c619ee295604ae2d.tar.bz2 ghdl-74faba8044d401ebe3d4ce62c619ee295604ae2d.zip | |
synth: handle conv_signed. Fix #2408
| -rw-r--r-- | src/synth/synth-vhdl_eval.adb | 4 | ||||
| -rw-r--r-- | src/synth/synth-vhdl_oper.adb | 7 |
2 files changed, 9 insertions, 2 deletions
diff --git a/src/synth/synth-vhdl_eval.adb b/src/synth/synth-vhdl_eval.adb index 020c67896..1913f349a 100644 --- a/src/synth/synth-vhdl_eval.adb +++ b/src/synth/synth-vhdl_eval.adb @@ -609,6 +609,7 @@ package body Synth.Vhdl_Eval is end case; end Eval_Vector_Minimum; + -- ARG to log-vector, sign extended. function Eval_To_Log_Vector (Arg : Uns64; Sz : Int64; Res_Type : Type_Acc) return Memtyp is @@ -2634,7 +2635,8 @@ package body Synth.Vhdl_Eval is (Uns64 (Read_Discrete (Param1)), Int64 (Param2.Typ.Abound.Len), Res_Typ); when Iir_Predefined_Ieee_Numeric_Std_Tosgn_Int_Nat_Sgn - | Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Vector_Int => + | Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Vector_Int + | Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Signed_Int => return Eval_To_Log_Vector (To_Uns64 (Read_Discrete (Param1)), Read_Discrete (Param2), Res_Typ); diff --git a/src/synth/synth-vhdl_oper.adb b/src/synth/synth-vhdl_oper.adb index d9f1c694e..64d2deae3 100644 --- a/src/synth/synth-vhdl_oper.adb +++ b/src/synth/synth-vhdl_oper.adb @@ -2039,7 +2039,8 @@ package body Synth.Vhdl_Oper is return Synth_Resize (Ctxt, L, B.Len, False, Expr); end; when Iir_Predefined_Ieee_Numeric_Std_Tosgn_Int_Nat_Sgn - | Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Vector_Int => + | Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Vector_Int + | Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Signed_Int => return Synth_Conv_Vector (True); when Iir_Predefined_Ieee_Numeric_Std_Toint_Uns_Nat | Iir_Predefined_Ieee_Numeric_Std_Unsigned_To_Integer_Slv_Nat @@ -2060,7 +2061,10 @@ package body Synth.Vhdl_Oper is | Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Vector_Uns | Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Uns | Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Log + | Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Signed_Log + | Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Signed_Uns | Iir_Predefined_Ieee_Std_Logic_Arith_Ext => + -- Unsigned to unsigned (resize) declare W : Width; begin @@ -2090,6 +2094,7 @@ package body Synth.Vhdl_Oper is when Iir_Predefined_Ieee_Numeric_Std_Resize_Sgn_Nat | Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Vector_Sgn | Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Unsigned_Sgn + | Iir_Predefined_Ieee_Std_Logic_Arith_Conv_Signed_Sgn | Iir_Predefined_Ieee_Std_Logic_Arith_Sxt => if not Is_Static (R.Val) then Error_Msg_Synth |