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| author | Patrick Lehmann <Patrick.Lehmann@plc2.de> | 2021-07-29 23:33:51 +0200 |
|---|---|---|
| committer | umarcor <unai.martinezcorral@ehu.eus> | 2021-08-23 16:35:33 +0200 |
| commit | 21a1a3b2ce0be2d9ada1c2d112d225f5d773f71a (patch) | |
| tree | 78e1431df1e7393112be9c4404b5ac208bdee34f | |
| parent | cfd625ab0a3d4df24bae77ed6143c44a53f26f49 (diff) | |
| download | ghdl-21a1a3b2ce0be2d9ada1c2d112d225f5d773f71a.tar.gz ghdl-21a1a3b2ce0be2d9ada1c2d112d225f5d773f71a.tar.bz2 ghdl-21a1a3b2ce0be2d9ada1c2d112d225f5d773f71a.zip | |
Added generate statements.
| -rw-r--r-- | testsuite/pyunit/Current.vhdl | 15 |
1 files changed, 14 insertions, 1 deletions
diff --git a/testsuite/pyunit/Current.vhdl b/testsuite/pyunit/Current.vhdl index 3c518cce4..d364a2b2e 100644 --- a/testsuite/pyunit/Current.vhdl +++ b/testsuite/pyunit/Current.vhdl @@ -81,7 +81,7 @@ architecture behav of entity_1 is disconnect address_bus : resolved_word after 3 ns; disconnect others : resolved_word after 2 ns; - default clock is rising_edge(clk); +-- default clock is rising_edge(clk); package inner_pack is end package; begin @@ -125,6 +125,19 @@ begin ); end block; + genIf: if True generate + constant G0 : boolean := False; + begin + + elsif False generate + constant G1 : boolean := False; + begin + + else generate + constant G2 : boolean := False; + begin + + end generate; end architecture behav; package package_1 is |