From 21a1a3b2ce0be2d9ada1c2d112d225f5d773f71a Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Thu, 29 Jul 2021 23:33:51 +0200 Subject: Added generate statements. --- testsuite/pyunit/Current.vhdl | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/testsuite/pyunit/Current.vhdl b/testsuite/pyunit/Current.vhdl index 3c518cce4..d364a2b2e 100644 --- a/testsuite/pyunit/Current.vhdl +++ b/testsuite/pyunit/Current.vhdl @@ -81,7 +81,7 @@ architecture behav of entity_1 is disconnect address_bus : resolved_word after 3 ns; disconnect others : resolved_word after 2 ns; - default clock is rising_edge(clk); +-- default clock is rising_edge(clk); package inner_pack is end package; begin @@ -125,6 +125,19 @@ begin ); end block; + genIf: if True generate + constant G0 : boolean := False; + begin + + elsif False generate + constant G1 : boolean := False; + begin + + else generate + constant G2 : boolean := False; + begin + + end generate; end architecture behav; package package_1 is -- cgit v1.2.3