synth: renaming and minor refactoring.

4 files changed, 43 insertions, 74 deletions

diff --git a/src/synth/synth-context.adb b/src/synth/synth-context.adb
index d05d45737..10eb12310 100644
--- a/src/synth/synth-context.adb
+++ b/src/synth/synth-context.adb
@@ -31,7 +31,6 @@ with Vhdl.Utils;
 with Netlists.Builders; use Netlists.Builders;
 with Netlists.Concats;
 
-with Synth.Errors; use Synth.Errors;
 with Synth.Expr; use Synth.Expr;
 
 package body Synth.Context is
@@ -174,41 +173,6 @@ package body Synth.Context is
       return Create_Value_Instance (Packages_Table.Last);
    end Create_Value_Instance;
 
-   function Alloc_Wire (Kind : Wire_Kind; Obj : Iir; Wtype : Type_Acc)
-                       return Value_Acc
-   is
-      Wire : Wire_Id;
-   begin
-      if Kind = Wire_None then
-         Wire := No_Wire_Id;
-      else
-         Wire := Alloc_Wire (Kind, Obj);
-      end if;
-      return Create_Value_Wire (Wire, Wtype);
-   end Alloc_Wire;
-
-   function Alloc_Object (Kind : Wire_Kind;
-                          Syn_Inst : Synth_Instance_Acc;
-                          Obj : Iir)
-                         return Value_Acc
-   is
-      Obj_Type : constant Iir := Get_Type (Obj);
-      Otype : Type_Acc;
-   begin
-      case Get_Kind (Obj_Type) is
-         when Iir_Kind_Enumeration_Type_Definition
-           | Iir_Kind_Enumeration_Subtype_Definition
-           | Iir_Kind_Array_Subtype_Definition
-           | Iir_Kind_Integer_Subtype_Definition
-           | Iir_Kind_Record_Type_Definition
-           | Iir_Kind_Record_Subtype_Definition =>
-            Otype := Get_Value_Type (Syn_Inst, Obj_Type);
-            return Alloc_Wire (Kind, Obj, Otype);
-         when others =>
-            Error_Kind ("alloc_object", Obj_Type);
-      end case;
-   end Alloc_Object;
-
    procedure Create_Object (Syn_Inst : Synth_Instance_Acc;
                             Slot : Object_Slot_Type;
                             Num : Object_Slot_Type := 1) is
@@ -227,7 +191,7 @@ package body Synth.Context is
    end Create_Object;
 
    procedure Create_Object_Force
-     (Syn_Inst : Synth_Instance_Acc; Decl : Iir; Val : Value_Acc)
+     (Syn_Inst : Synth_Instance_Acc; Decl : Node; Val : Value_Acc)
    is
       Info : constant Sim_Info_Acc := Get_Info (Decl);
    begin
@@ -236,7 +200,7 @@ package body Synth.Context is
    end Create_Object_Force;
 
    procedure Create_Object
-     (Syn_Inst : Synth_Instance_Acc; Decl : Iir; Val : Value_Acc)
+     (Syn_Inst : Synth_Instance_Acc; Decl : Node; Val : Value_Acc)
    is
       Info : constant Sim_Info_Acc := Get_Info (Decl);
    begin
@@ -245,7 +209,7 @@ package body Synth.Context is
    end Create_Object;
 
    procedure Create_Package_Object
-     (Syn_Inst : Synth_Instance_Acc; Decl : Iir; Val : Value_Acc)
+     (Syn_Inst : Synth_Instance_Acc; Decl : Node; Val : Value_Acc)
    is
       Info : constant Sim_Info_Acc := Get_Info (Decl);
    begin
@@ -254,7 +218,7 @@ package body Synth.Context is
    end Create_Package_Object;
 
    procedure Destroy_Object
-     (Syn_Inst : Synth_Instance_Acc; Decl : Iir)
+     (Syn_Inst : Synth_Instance_Acc; Decl : Node)
    is
       Info : constant Sim_Info_Acc := Get_Info (Decl);
       Slot : constant Object_Slot_Type := Info.Slot;
@@ -268,21 +232,24 @@ package body Synth.Context is
       Syn_Inst.Elab_Objects := Slot - 1;
    end Destroy_Object;
 
-   procedure Make_Object (Syn_Inst : Synth_Instance_Acc;
-                          Kind : Wire_Kind;
-                          Obj : Iir)
+   procedure Create_Wire_Object (Syn_Inst : Synth_Instance_Acc;
+                                 Kind : Wire_Kind;
+                                 Obj : Node)
    is
-      Otype : constant Iir := Get_Type (Obj);
+      Obj_Type : constant Node := Get_Type (Obj);
+      Otyp : constant Type_Acc := Get_Value_Type (Syn_Inst, Obj_Type);
       Val : Value_Acc;
+      Wid : Wire_Id;
    begin
-      Val := Alloc_Object (Kind, Syn_Inst, Obj);
-      if Val = null then
-         Error_Msg_Synth (+Obj, "%n is not supported", +Otype);
-         return;
+      if Kind = Wire_None then
+         Wid := No_Wire_Id;
+      else
+         Wid := Alloc_Wire (Kind, Obj);
       end if;
+      Val := Create_Value_Wire (Wid, Otyp);
 
       Create_Object (Syn_Inst, Obj, Val);
-   end Make_Object;
+   end Create_Wire_Object;
 
    function Get_Instance_By_Scope
      (Syn_Inst: Synth_Instance_Acc; Scope: Sim_Info_Acc)
@@ -326,7 +293,7 @@ package body Synth.Context is
       end case;
    end Get_Instance_By_Scope;
 
-   function Get_Value (Syn_Inst: Synth_Instance_Acc; Obj : Iir)
+   function Get_Value (Syn_Inst: Synth_Instance_Acc; Obj : Node)
                       return Value_Acc
    is
       Info : constant Sim_Info_Acc := Get_Info (Obj);
@@ -336,7 +303,7 @@ package body Synth.Context is
       return Obj_Inst.Objects (Info.Slot);
    end Get_Value;
 
-   function Get_Value_Type (Syn_Inst : Synth_Instance_Acc; Atype : Iir)
+   function Get_Value_Type (Syn_Inst : Synth_Instance_Acc; Atype : Node)
                            return Type_Acc
    is
       Val : Value_Acc;
diff --git a/src/synth/synth-context.ads b/src/synth/synth-context.ads
index a652e9ba3..182cfa5d5 100644
--- a/src/synth/synth-context.ads
+++ b/src/synth/synth-context.ads
@@ -73,30 +73,30 @@ package Synth.Context is
    procedure Set_Instance_Const (Inst : Synth_Instance_Acc; Val : Boolean);
 
    procedure Create_Object
-     (Syn_Inst : Synth_Instance_Acc; Decl : Iir; Val : Value_Acc);
+     (Syn_Inst : Synth_Instance_Acc; Decl : Node; Val : Value_Acc);
 
    procedure Create_Package_Object
-     (Syn_Inst : Synth_Instance_Acc; Decl : Iir; Val : Value_Acc);
+     (Syn_Inst : Synth_Instance_Acc; Decl : Node; Val : Value_Acc);
 
    --  Force the value of DECL, without checking for elaboration order.
    --  It is for deferred constants.
    procedure Create_Object_Force
-     (Syn_Inst : Synth_Instance_Acc; Decl : Iir; Val : Value_Acc);
+     (Syn_Inst : Synth_Instance_Acc; Decl : Node; Val : Value_Acc);
 
    procedure Destroy_Object
-     (Syn_Inst : Synth_Instance_Acc; Decl : Iir);
+     (Syn_Inst : Synth_Instance_Acc; Decl : Node);
 
    --  Build the value for object OBJ.
    --  KIND must be Wire_Variable or Wire_Signal.
-   procedure Make_Object (Syn_Inst : Synth_Instance_Acc;
-                          Kind : Wire_Kind;
-                          Obj : Iir);
+   procedure Create_Wire_Object (Syn_Inst : Synth_Instance_Acc;
+                                 Kind : Wire_Kind;
+                                 Obj : Node);
 
    --  Get the value of OBJ.
-   function Get_Value (Syn_Inst : Synth_Instance_Acc; Obj : Iir)
+   function Get_Value (Syn_Inst : Synth_Instance_Acc; Obj : Node)
                       return Value_Acc;
    --  Wrapper around Get_Value for types.
-   function Get_Value_Type (Syn_Inst : Synth_Instance_Acc; Atype : Iir)
+   function Get_Value_Type (Syn_Inst : Synth_Instance_Acc; Atype : Node)
                            return Type_Acc;
 
    --  Get a net from a scalar/vector value.  This will automatically create
diff --git a/src/synth/synth-decls.adb b/src/synth/synth-decls.adb
index 61b2e23c4..83626b6c4 100644
--- a/src/synth/synth-decls.adb
+++ b/src/synth/synth-decls.adb
@@ -518,7 +518,7 @@ package body Synth.Decls is
                   pragma Assert (Init /= null);
                   Create_Object (Syn_Inst, Decl, Init);
                else
-                  Make_Object (Syn_Inst, Wire_Variable, Decl);
+                  Create_Wire_Object (Syn_Inst, Wire_Variable, Decl);
                   Create_Var_Wire (Syn_Inst, Decl, Init);
                   if Is_Subprg and then Init /= null then
                      Phi_Assign
@@ -529,7 +529,7 @@ package body Synth.Decls is
             end;
          when Iir_Kind_Interface_Variable_Declaration =>
             --  Ignore default value.
-            Make_Object (Syn_Inst, Wire_Variable, Decl);
+            Create_Wire_Object (Syn_Inst, Wire_Variable, Decl);
             Create_Var_Wire (Syn_Inst, Decl, null);
          when Iir_Kind_Constant_Declaration =>
             Synth_Constant_Declaration (Syn_Inst, Decl);
@@ -541,7 +541,7 @@ package body Synth.Decls is
                Init : Value_Acc;
                Obj_Type : Type_Acc;
             begin
-               Make_Object (Syn_Inst, Wire_Signal, Decl);
+               Create_Wire_Object (Syn_Inst, Wire_Signal, Decl);
                if Is_Valid (Def) then
                   Obj_Type := Get_Value_Type (Syn_Inst, Get_Type (Decl));
                   Init := Synth_Expression_With_Type (Syn_Inst, Def, Obj_Type);
@@ -567,7 +567,7 @@ package body Synth.Decls is
                Create_Object (Syn_Inst, Decl, Res);
             end;
          when Iir_Kind_Anonymous_Signal_Declaration =>
-            Make_Object (Syn_Inst, Wire_Signal, Decl);
+            Create_Wire_Object (Syn_Inst, Wire_Signal, Decl);
             Create_Var_Wire (Syn_Inst, Decl, null);
          when Iir_Kind_Procedure_Declaration
            | Iir_Kind_Function_Declaration =>
diff --git a/src/synth/synth-insts.adb b/src/synth/synth-insts.adb
index 656db9e58..cdd917536 100644
--- a/src/synth/synth-insts.adb
+++ b/src/synth/synth-insts.adb
@@ -178,11 +178,11 @@ package body Synth.Insts is
          Synth_Declaration_Type (Syn_Inst, Inter);
          case Mode_To_Port_Kind (Get_Mode (Inter)) is
             when Port_In =>
-               Make_Object (Syn_Inst, Wire_None, Inter);
+               Create_Wire_Object (Syn_Inst, Wire_None, Inter);
                Nbr_Inputs := Nbr_Inputs + 1;
             when Port_Out
               | Port_Inout =>
-               Make_Object (Syn_Inst, Wire_None, Inter);
+               Create_Wire_Object (Syn_Inst, Wire_None, Inter);
                Nbr_Outputs := Nbr_Outputs + 1;
          end case;
          Inter := Get_Chain (Inter);
@@ -274,18 +274,20 @@ package body Synth.Insts is
 
          case Mode_To_Port_Kind (Get_Mode (Inter)) is
             when Port_In =>
-               Connect
-                 (Get_Input (Inst, Nbr_Inputs),
-                  Get_Net (Synth_Expression (Syn_Inst, Actual)));
+               --  Connect the net to the input.
+               Connect (Get_Input (Inst, Nbr_Inputs),
+                        Get_Net (Synth_Expression (Syn_Inst, Actual)));
                Nbr_Inputs := Nbr_Inputs + 1;
             when Port_Out
               | Port_Inout =>
                if Actual /= Null_Iir then
+                  --  Create a port gate (so that is has a name).
                   Port := Get_Output (Inst, Nbr_Outputs);
                   Port := Builders.Build_Port (Get_Build (Syn_Inst), Port);
                   O := Create_Value_Net
                     (Port, Get_Value_Type (Inst_Obj.Syn_Inst,
                                            Get_Type (Inter)));
+                  --  Assign the port output to the actual (a net).
                   Synth_Assignment (Syn_Inst, Actual, O, Assoc);
                end if;
                Nbr_Outputs := Nbr_Outputs + 1;
@@ -332,10 +334,10 @@ package body Synth.Insts is
          Synth_Declaration_Type (Sub_Inst, Inter);
          case Mode_To_Port_Kind (Get_Mode (Inter)) is
             when Port_In =>
-               Make_Object (Sub_Inst, Wire_None, Inter);
+               Create_Wire_Object (Sub_Inst, Wire_None, Inter);
             when Port_Out
               | Port_Inout =>
-               Make_Object (Sub_Inst, Wire_None, Inter);
+               Create_Wire_Object (Sub_Inst, Wire_None, Inter);
          end case;
          Inter := Get_Chain (Inter);
       end loop;
@@ -480,7 +482,7 @@ package body Synth.Insts is
                                    (Syn_Inst, Actual, Inter_Type));
                when Port_Out
                  | Port_Inout =>
-                  Make_Object (Comp_Inst, Wire_None, Assoc_Inter);
+                  Create_Wire_Object (Comp_Inst, Wire_None, Assoc_Inter);
                   Create_Component_Wire
                     (Assoc_Inter, Get_Value (Comp_Inst, Assoc_Inter));
             end case;
@@ -621,10 +623,10 @@ package body Synth.Insts is
          Synth_Declaration_Type (Syn_Inst, Inter);
          case Mode_To_Port_Kind (Get_Mode (Inter)) is
             when Port_In =>
-               Make_Object (Syn_Inst, Wire_None, Inter);
+               Create_Wire_Object (Syn_Inst, Wire_None, Inter);
             when Port_Out
               | Port_Inout =>
-               Make_Object (Syn_Inst, Wire_None, Inter);
+               Create_Wire_Object (Syn_Inst, Wire_None, Inter);
          end case;
          Inter := Get_Chain (Inter);
       end loop;